fetch_impl.hh (8137:48371b9fb929) fetch_impl.hh (8138:f08692f2932e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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810 }
811
812 return Inactive;
813}
814
815template <class Impl>
816void
817DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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810 }
811
812 return Inactive;
813}
814
815template <class Impl>
816void
817DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
818 const InstSeqNum &seq_num, ThreadID tid)
818 const InstSeqNum &seq_num, DynInstPtr &squashInst,
819 ThreadID tid)
819{
820 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
821
822 doSquash(newPC, tid);
820{
821 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
822
823 doSquash(newPC, tid);
824 if (squashInst)
825 predecoder.reset(squashInst->staticInst->machInst);
823
824 // Tell the CPU to remove any instructions that are not in the ROB.
825 cpu->removeInstsNotInROB(tid);
826}
827
828template <class Impl>
829void
830DefaultFetch<Impl>::tick()

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827 // Tell the CPU to remove any instructions that are not in the ROB.
828 cpu->removeInstsNotInROB(tid);
829}
830
831template <class Impl>
832void
833DefaultFetch<Impl>::tick()

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