fetch_impl.hh (7963:6d955240bb62) fetch_impl.hh (8064:5b111ae7e7d4)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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263 "bad addresses, or out of MSHRs")
264 .prereq(fetchMiscStallCycles);
265
266 fetchIcacheSquashes
267 .name(name() + ".IcacheSquashes")
268 .desc("Number of outstanding Icache misses that were squashed")
269 .prereq(fetchIcacheSquashes);
270
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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263 "bad addresses, or out of MSHRs")
264 .prereq(fetchMiscStallCycles);
265
266 fetchIcacheSquashes
267 .name(name() + ".IcacheSquashes")
268 .desc("Number of outstanding Icache misses that were squashed")
269 .prereq(fetchIcacheSquashes);
270
271 fetchTlbSquashes
272 .name(name() + ".ItlbSquashes")
273 .desc("Number of outstanding ITLB misses that were squashed")
274 .prereq(fetchTlbSquashes);
275
271 fetchNisnDist
272 .init(/* base value */ 0,
273 /* last value */ fetchWidth,
274 /* bucket size */ 1)
275 .name(name() + ".rateDist")
276 .desc("Number of instructions fetched each cycle (Total)")
277 .flags(Stats::pdf);
278

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575 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
576 tid);
577 return false;
578 }
579
580 // Align the fetch address so it's at the start of a cache block.
581 Addr block_PC = icacheBlockAlignPC(vaddr);
582
276 fetchNisnDist
277 .init(/* base value */ 0,
278 /* last value */ fetchWidth,
279 /* bucket size */ 1)
280 .name(name() + ".rateDist")
281 .desc("Number of instructions fetched each cycle (Total)")
282 .flags(Stats::pdf);
283

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580 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
581 tid);
582 return false;
583 }
584
585 // Align the fetch address so it's at the start of a cache block.
586 Addr block_PC = icacheBlockAlignPC(vaddr);
587
588 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
589 tid, block_PC, vaddr);
590
583 // Setup the memReq to do a read of the first instruction's address.
584 // Set the appropriate read size and flags as well.
585 // Build request here.
586 RequestPtr mem_req =
587 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
588 pc, cpu->thread[tid]->contextId(), tid);
589
590 memReq[tid] = mem_req;

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602DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
603{
604 ThreadID tid = mem_req->threadId();
605 Addr block_PC = mem_req->getVaddr();
606
607 // Wake up CPU if it was idle
608 cpu->wakeCPU();
609
591 // Setup the memReq to do a read of the first instruction's address.
592 // Set the appropriate read size and flags as well.
593 // Build request here.
594 RequestPtr mem_req =
595 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
596 pc, cpu->thread[tid]->contextId(), tid);
597
598 memReq[tid] = mem_req;

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610DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
611{
612 ThreadID tid = mem_req->threadId();
613 Addr block_PC = mem_req->getVaddr();
614
615 // Wake up CPU if it was idle
616 cpu->wakeCPU();
617
618 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
619 mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) {
620 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
621 tid);
622 ++fetchTlbSquashes;
623 delete mem_req;
624 return;
625 }
626
627
610 // If translation was successful, attempt to read the icache block.
611 if (fault == NoFault) {
612 // Build packet here.
613 PacketPtr data_pkt = new Packet(mem_req,
614 MemCmd::ReadReq, Packet::Broadcast);
615 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
616
617 cacheDataPC[tid] = block_PC;

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634 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
635 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
636 "response.\n", tid);
637
638 lastIcacheStall[tid] = curTick();
639 fetchStatus[tid] = IcacheWaitResponse;
640 }
641 } else {
628 // If translation was successful, attempt to read the icache block.
629 if (fault == NoFault) {
630 // Build packet here.
631 PacketPtr data_pkt = new Packet(mem_req,
632 MemCmd::ReadReq, Packet::Broadcast);
633 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
634
635 cacheDataPC[tid] = block_PC;

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652 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
653 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
654 "response.\n", tid);
655
656 lastIcacheStall[tid] = curTick();
657 fetchStatus[tid] = IcacheWaitResponse;
658 }
659 } else {
660 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
661 mem_req->getVaddr(), memReq[tid]->getVaddr());
642 // Translation faulted, icache request won't be sent.
643 delete mem_req;
644 memReq[tid] = NULL;
645
646 // Send the fault to commit. This thread will not do anything
647 // until commit handles the fault. The only other way it can
648 // wake up is if a squash comes along and changes the PC.
649 TheISA::PCState fetchPC = pc[tid];
650
662 // Translation faulted, icache request won't be sent.
663 delete mem_req;
664 memReq[tid] = NULL;
665
666 // Send the fault to commit. This thread will not do anything
667 // until commit handles the fault. The only other way it can
668 // wake up is if a squash comes along and changes the PC.
669 TheISA::PCState fetchPC = pc[tid];
670
671 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
651 // We will use a nop in ordier to carry the fault.
652 DynInstPtr instruction = buildInst(tid,
653 StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()),
654 NULL, fetchPC, fetchPC, false);
655
656 instruction->setPredTarg(fetchPC);
657 instruction->fault = fault;
658 wroteToTimeBuffer = true;

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681 macroop[tid] = NULL;
682 predecoder.reset();
683
684 // Clear the icache miss if it's outstanding.
685 if (fetchStatus[tid] == IcacheWaitResponse) {
686 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
687 tid);
688 memReq[tid] = NULL;
672 // We will use a nop in ordier to carry the fault.
673 DynInstPtr instruction = buildInst(tid,
674 StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()),
675 NULL, fetchPC, fetchPC, false);
676
677 instruction->setPredTarg(fetchPC);
678 instruction->fault = fault;
679 wroteToTimeBuffer = true;

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702 macroop[tid] = NULL;
703 predecoder.reset();
704
705 // Clear the icache miss if it's outstanding.
706 if (fetchStatus[tid] == IcacheWaitResponse) {
707 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
708 tid);
709 memReq[tid] = NULL;
710 } else if (fetchStatus[tid] == ItlbWait) {
711 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
712 tid);
713 memReq[tid] = NULL;
689 }
690
691 // Get rid of the retrying packet if it was from this thread.
692 if (retryTid == tid) {
693 assert(cacheBlocked);
694 if (retryPkt) {
695 delete retryPkt->req;
696 delete retryPkt;

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1115 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1116 ++icacheStallCycles;
1117 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1118 tid);
1119 } else if (fetchStatus[tid] == ItlbWait) {
1120 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1121 "finish! \n", tid);
1122 ++fetchTlbCycles;
714 }
715
716 // Get rid of the retrying packet if it was from this thread.
717 if (retryTid == tid) {
718 assert(cacheBlocked);
719 if (retryPkt) {
720 delete retryPkt->req;
721 delete retryPkt;

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1140 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1141 ++icacheStallCycles;
1142 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1143 tid);
1144 } else if (fetchStatus[tid] == ItlbWait) {
1145 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1146 "finish! \n", tid);
1147 ++fetchTlbCycles;
1148 } else if (fetchStatus[tid] == TrapPending) {
1149 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n",
1150 tid);
1123 }
1124
1151 }
1152
1153
1125 // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse
1126 // so fetch should do nothing.
1127 return;
1128 }
1129
1130 ++fetchCycles;
1131
1132 TheISA::PCState nextPC = thisPC;

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1155 // so fetch should do nothing.
1156 return;
1157 }
1158
1159 ++fetchCycles;
1160
1161 TheISA::PCState nextPC = thisPC;

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