fetch_impl.hh (7764:03efcdc3421f) fetch_impl.hh (7823:dac01f14f20f)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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63 fetch->setIcache();
64}
65
66template<class Impl>
67Tick
68DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
69{
70 panic("DefaultFetch doesn't expect recvAtomic callback!");
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 54 unchanged lines hidden (view full) ---

63 fetch->setIcache();
64}
65
66template<class Impl>
67Tick
68DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
69{
70 panic("DefaultFetch doesn't expect recvAtomic callback!");
71 return curTick;
71 return curTick();
72}
73
74template<class Impl>
75void
76DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
77{
78 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
79 "functional call.");

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620 retryPkt = data_pkt;
621 retryTid = tid;
622 cacheBlocked = true;
623 return false;
624 }
625
626 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
627
72}
73
74template<class Impl>
75void
76DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
77{
78 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
79 "functional call.");

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620 retryPkt = data_pkt;
621 retryTid = tid;
622 cacheBlocked = true;
623 return false;
624 }
625
626 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
627
628 lastIcacheStall[tid] = curTick;
628 lastIcacheStall[tid] = curTick();
629
630 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
631 "response.\n", tid);
632
633 fetchStatus[tid] = IcacheWaitResponse;
634 } else {
635 delete mem_req;
636 memReq[tid] = NULL;

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987
988 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
989 instruction->staticInst->
990 disassemble(thisPC.instAddr()));
991
992#if TRACING_ON
993 if (trace) {
994 instruction->traceData =
629
630 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
631 "response.\n", tid);
632
633 fetchStatus[tid] = IcacheWaitResponse;
634 } else {
635 delete mem_req;
636 memReq[tid] = NULL;

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987
988 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
989 instruction->staticInst->
990 disassemble(thisPC.instAddr()));
991
992#if TRACING_ON
993 if (trace) {
994 instruction->traceData =
995 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
995 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
996 instruction->staticInst, thisPC, curMacroop);
997 }
998#else
999 instruction->traceData = NULL;
1000#endif
1001
1002 // Add instruction to the CPU's list of instructions.
1003 instruction->setInstListIt(cpu->addInst(instruction));

--- 428 unchanged lines hidden --- 		996 instruction->staticInst, thisPC, curMacroop);
997 }
998#else
999 instruction->traceData = NULL;
1000#endif
1001
1002 // Add instruction to the CPU's list of instructions.
1003 instruction->setInstListIt(cpu->addInst(instruction));

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