fetch_impl.hh (7616:1a0ab2308bbe) fetch_impl.hh (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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311}
312
313template<class Impl>
314void
315DefaultFetch<Impl>::initStage()
316{
317 // Setup PC and nextPC with initial state.
318 for (ThreadID tid = 0; tid < numThreads; tid++) {
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 302 unchanged lines hidden (view full) ---

311}
312
313template<class Impl>
314void
315DefaultFetch<Impl>::initStage()
316{
317 // Setup PC and nextPC with initial state.
318 for (ThreadID tid = 0; tid < numThreads; tid++) {
319 PC[tid] = cpu->readPC(tid);
320 nextPC[tid] = cpu->readNextPC(tid);
321 microPC[tid] = cpu->readMicroPC(tid);
319 pc[tid] = cpu->pcState(tid);
322 }
323
324 for (ThreadID tid = 0; tid < numThreads; tid++) {
325
326 fetchStatus[tid] = Running;
327
328 priorityList.push_back(tid);
329

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440DefaultFetch<Impl>::takeOverFrom()
441{
442 // Reset all state
443 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
444 stalls[i].decode = 0;
445 stalls[i].rename = 0;
446 stalls[i].iew = 0;
447 stalls[i].commit = 0;
320 }
321
322 for (ThreadID tid = 0; tid < numThreads; tid++) {
323
324 fetchStatus[tid] = Running;
325
326 priorityList.push_back(tid);
327

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438DefaultFetch<Impl>::takeOverFrom()
439{
440 // Reset all state
441 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
442 stalls[i].decode = 0;
443 stalls[i].rename = 0;
444 stalls[i].iew = 0;
445 stalls[i].commit = 0;
448 PC[i] = cpu->readPC(i);
449 nextPC[i] = cpu->readNextPC(i);
450 microPC[i] = cpu->readMicroPC(i);
446 pc[i] = cpu->pcState(i);
451 fetchStatus[i] = Running;
452 }
453 numInst = 0;
454 wroteToTimeBuffer = false;
455 _status = Inactive;
456 switchedOut = false;
457 interruptPending = false;
458 branchPred.takeOverFrom();

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491 cpu->deactivateStage(O3CPU::FetchIdx);
492
493 _status = Inactive;
494 }
495}
496
497template <class Impl>
498bool
447 fetchStatus[i] = Running;
448 }
449 numInst = 0;
450 wroteToTimeBuffer = false;
451 _status = Inactive;
452 switchedOut = false;
453 interruptPending = false;
454 branchPred.takeOverFrom();

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487 cpu->deactivateStage(O3CPU::FetchIdx);
488
489 _status = Inactive;
490 }
491}
492
493template <class Impl>
494bool
499DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
500 Addr &next_NPC, Addr &next_MicroPC)
495DefaultFetch::lookupAndUpdateNextPC(
496 DynInstPtr &inst, TheISA::PCState &nextPC)
501{
502 // Do branch prediction check here.
503 // A bit of a misnomer...next_PC is actually the current PC until
504 // this function updates it.
505 bool predict_taken;
506
507 if (!inst->isControl()) {
497{
498 // Do branch prediction check here.
499 // A bit of a misnomer...next_PC is actually the current PC until
500 // this function updates it.
501 bool predict_taken;
502
503 if (!inst->isControl()) {
508 if (inst->isMicroop() && !inst->isLastMicroop()) {
509 next_MicroPC++;
510 } else {
511 next_PC = next_NPC;
512 next_NPC = next_NPC + instSize;
513 next_MicroPC = 0;
514 }
515 inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
504 TheISA::advancePC(nextPC, inst->staticInst);
505 inst->setPredTarg(nextPC);
516 inst->setPredTaken(false);
517 return false;
518 }
519
506 inst->setPredTaken(false);
507 return false;
508 }
509
520 //Assume for now that all control flow is to a different macroop which
521 //would reset the micro pc to 0.
522 next_MicroPC = 0;
523
524 ThreadID tid = inst->threadNumber;
510 ThreadID tid = inst->threadNumber;
525 Addr pred_PC = next_PC;
526 predict_taken = branchPred.predict(inst, pred_PC, tid);
511 predict_taken = branchPred.predict(inst, nextPC, tid);
527
528 if (predict_taken) {
512
513 if (predict_taken) {
529 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %#x.\n",
530 tid, inst->seqNum, pred_PC);
514 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n",
515 tid, inst->seqNum, nextPC);
531 } else {
532 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
533 tid, inst->seqNum);
534 }
535
516 } else {
517 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
518 tid, inst->seqNum);
519 }
520
536#if ISA_HAS_DELAY_SLOT
537 next_PC = next_NPC;
538 if (predict_taken)
539 next_NPC = pred_PC;
540 else
541 next_NPC += instSize;
542#else
543 if (predict_taken)
544 next_PC = pred_PC;
545 else
546 next_PC += instSize;
547 next_NPC = next_PC + instSize;
548#endif
549
550 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %#x and then %#x.\n",
551 tid, inst->seqNum, next_PC, next_NPC);
552 inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
521 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
522 tid, inst->seqNum, nextPC);
523 inst->setPredTarg(nextPC);
553 inst->setPredTaken(predict_taken);
554
555 ++fetchedBranches;
556
557 if (predict_taken) {
558 ++predictedBranches;
559 }
560

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663 }
664
665 ret_fault = fault;
666 return true;
667}
668
669template <class Impl>
670inline void
524 inst->setPredTaken(predict_taken);
525
526 ++fetchedBranches;
527
528 if (predict_taken) {
529 ++predictedBranches;
530 }
531

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634 }
635
636 ret_fault = fault;
637 return true;
638}
639
640template <class Impl>
641inline void
671DefaultFetch<Impl>::doSquash(const Addr &new_PC,
672 const Addr &new_NPC, const Addr &new_microPC, ThreadID tid)
642DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
673{
643{
674 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
675 tid, new_PC, new_NPC);
644 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
645 tid, newPC);
676
646
677 PC[tid] = new_PC;
678 nextPC[tid] = new_NPC;
679 microPC[tid] = new_microPC;
647 pc[tid] = newPC;
680
681 // Clear the icache miss if it's outstanding.
682 if (fetchStatus[tid] == IcacheWaitResponse) {
683 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
684 tid);
685 memReq[tid] = NULL;
686 }
687

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698
699 fetchStatus[tid] = Squashing;
700
701 ++fetchSquashCycles;
702}
703
704template<class Impl>
705void
648
649 // Clear the icache miss if it's outstanding.
650 if (fetchStatus[tid] == IcacheWaitResponse) {
651 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
652 tid);
653 memReq[tid] = NULL;
654 }
655

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666
667 fetchStatus[tid] = Squashing;
668
669 ++fetchSquashCycles;
670}
671
672template<class Impl>
673void
706DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
707 const Addr &new_MicroPC,
674DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
708 const InstSeqNum &seq_num, ThreadID tid)
709{
675 const InstSeqNum &seq_num, ThreadID tid)
676{
710 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
677 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
711
678
712 doSquash(new_PC, new_NPC, new_MicroPC, tid);
679 doSquash(newPC, tid);
713
714 // Tell the CPU to remove any instructions that are in flight between
715 // fetch and decode.
716 cpu->removeInstsUntil(seq_num, tid);
717}
718
719template<class Impl>
720bool

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779 cpu->deactivateStage(O3CPU::FetchIdx);
780 }
781
782 return Inactive;
783}
784
785template <class Impl>
786void
680
681 // Tell the CPU to remove any instructions that are in flight between
682 // fetch and decode.
683 cpu->removeInstsUntil(seq_num, tid);
684}
685
686template<class Impl>
687bool

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746 cpu->deactivateStage(O3CPU::FetchIdx);
747 }
748
749 return Inactive;
750}
751
752template <class Impl>
753void
787DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
788 const Addr &new_MicroPC,
754DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
789 const InstSeqNum &seq_num, ThreadID tid)
790{
755 const InstSeqNum &seq_num, ThreadID tid)
756{
791 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
757 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
792
758
793 doSquash(new_PC, new_NPC, new_MicroPC, tid);
759 doSquash(newPC, tid);
794
795 // Tell the CPU to remove any instructions that are not in the ROB.
796 cpu->removeInstsNotInROB(tid);
797}
798
799template <class Impl>
800void
801DefaultFetch<Impl>::tick()

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898 }
899
900 // Check squash signals from commit.
901 if (fromCommit->commitInfo[tid].squash) {
902
903 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
904 "from commit.\n",tid);
905 // In any case, squash.
760
761 // Tell the CPU to remove any instructions that are not in the ROB.
762 cpu->removeInstsNotInROB(tid);
763}
764
765template <class Impl>
766void
767DefaultFetch<Impl>::tick()

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864 }
865
866 // Check squash signals from commit.
867 if (fromCommit->commitInfo[tid].squash) {
868
869 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
870 "from commit.\n",tid);
871 // In any case, squash.
906 squash(fromCommit->commitInfo[tid].nextPC,
907 fromCommit->commitInfo[tid].nextNPC,
908 fromCommit->commitInfo[tid].nextMicroPC,
872 squash(fromCommit->commitInfo[tid].pc,
909 fromCommit->commitInfo[tid].doneSeqNum,
910 tid);
911
912 // Also check if there's a mispredict that happened.
913 if (fromCommit->commitInfo[tid].branchMispredict) {
914 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
873 fromCommit->commitInfo[tid].doneSeqNum,
874 tid);
875
876 // Also check if there's a mispredict that happened.
877 if (fromCommit->commitInfo[tid].branchMispredict) {
878 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
915 fromCommit->commitInfo[tid].nextPC,
879 fromCommit->commitInfo[tid].pc,
916 fromCommit->commitInfo[tid].branchTaken,
917 tid);
918 } else {
919 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
920 tid);
921 }
922
923 return true;

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950 tid);
951 } else {
952 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
953 tid);
954 }
955
956 if (fetchStatus[tid] != Squashing) {
957
880 fromCommit->commitInfo[tid].branchTaken,
881 tid);
882 } else {
883 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
884 tid);
885 }
886
887 return true;

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914 tid);
915 } else {
916 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
917 tid);
918 }
919
920 if (fetchStatus[tid] != Squashing) {
921
958 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
959 fromDecode->decodeInfo[tid].nextPC,
960 fromDecode->decodeInfo[tid].nextNPC);
922 TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
923 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
961 // Squash unless we're already squashing
962 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
924 // Squash unless we're already squashing
925 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
963 fromDecode->decodeInfo[tid].nextNPC,
964 fromDecode->decodeInfo[tid].nextMicroPC,
965 fromDecode->decodeInfo[tid].doneSeqNum,
966 tid);
967
968 return true;
969 }
970 }
971
972 if (checkStall(tid) &&

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1011 // Breaks looping condition in tick()
1012 threadFetched = numFetchingThreads;
1013 return;
1014 }
1015
1016 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1017
1018 // The current PC.
926 fromDecode->decodeInfo[tid].doneSeqNum,
927 tid);
928
929 return true;
930 }
931 }
932
933 if (checkStall(tid) &&

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972 // Breaks looping condition in tick()
973 threadFetched = numFetchingThreads;
974 return;
975 }
976
977 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
978
979 // The current PC.
1019 Addr fetch_PC = PC[tid];
1020 Addr fetch_NPC = nextPC[tid];
1021 Addr fetch_MicroPC = microPC[tid];
980 TheISA::PCState fetchPC = pc[tid];
1022
1023 // Fault code for memory access.
1024 Fault fault = NoFault;
1025
1026 // If returning from the delay of a cache miss, then update the status
1027 // to running, otherwise do the cache access. Possibly move this up
1028 // to tick() function.
1029 if (fetchStatus[tid] == IcacheAccessComplete) {
1030 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1031 tid);
1032
1033 fetchStatus[tid] = Running;
1034 status_change = true;
1035 } else if (fetchStatus[tid] == Running) {
1036 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
981
982 // Fault code for memory access.
983 Fault fault = NoFault;
984
985 // If returning from the delay of a cache miss, then update the status
986 // to running, otherwise do the cache access. Possibly move this up
987 // to tick() function.
988 if (fetchStatus[tid] == IcacheAccessComplete) {
989 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
990 tid);
991
992 fetchStatus[tid] = Running;
993 status_change = true;
994 } else if (fetchStatus[tid] == Running) {
995 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1037 "instruction, starting at PC %08p.\n",
1038 tid, fetch_PC);
996 "instruction, starting at PC %s.\n", tid, fetchPC);
1039
997
1040 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
998 bool fetch_success = fetchCacheLine(fetchPC.instAddr(), fault, tid);
1041 if (!fetch_success) {
1042 if (cacheBlocked) {
1043 ++icacheStallCycles;
1044 } else {
1045 ++fetchMiscStallCycles;
1046 }
1047 return;
1048 }

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1070
1071 // If we had a stall due to an icache miss, then return.
1072 if (fetchStatus[tid] == IcacheWaitResponse) {
1073 ++icacheStallCycles;
1074 status_change = true;
1075 return;
1076 }
1077
999 if (!fetch_success) {
1000 if (cacheBlocked) {
1001 ++icacheStallCycles;
1002 } else {
1003 ++fetchMiscStallCycles;
1004 }
1005 return;
1006 }

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1028
1029 // If we had a stall due to an icache miss, then return.
1030 if (fetchStatus[tid] == IcacheWaitResponse) {
1031 ++icacheStallCycles;
1032 status_change = true;
1033 return;
1034 }
1035
1078 Addr next_PC = fetch_PC;
1079 Addr next_NPC = fetch_NPC;
1080 Addr next_MicroPC = fetch_MicroPC;
1036 TheISA::PCState nextPC = fetchPC;
1081
1082 InstSeqNum inst_seq;
1083 MachInst inst;
1084 ExtMachInst ext_inst;
1037
1038 InstSeqNum inst_seq;
1039 MachInst inst;
1040 ExtMachInst ext_inst;
1085 // @todo: Fix this hack.
1086 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1087
1088 StaticInstPtr staticInst = NULL;
1089 StaticInstPtr macroop = NULL;
1090
1091 if (fault == NoFault) {
1041
1042 StaticInstPtr staticInst = NULL;
1043 StaticInstPtr macroop = NULL;
1044
1045 if (fault == NoFault) {
1046 //XXX Masking out pal mode bit. This will break x86. Alpha needs
1047 //to pull the pal mode bit ouf ot the instruction address.
1048 unsigned offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid];
1049 assert(offset < cacheBlkSize);
1050
1092 // If the read of the first instruction was successful, then grab the
1093 // instructions from the rest of the cache line and put them into the
1094 // queue heading to decode.
1095
1096 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1097 "decode.\n",tid);
1098
1099 // Need to keep track of whether or not a predicted branch
1100 // ended this fetch block.
1101 bool predicted_branch = false;
1102
1103 while (offset < cacheBlkSize &&
1104 numInst < fetchWidth &&
1105 !predicted_branch) {
1106
1051 // If the read of the first instruction was successful, then grab the
1052 // instructions from the rest of the cache line and put them into the
1053 // queue heading to decode.
1054
1055 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1056 "decode.\n",tid);
1057
1058 // Need to keep track of whether or not a predicted branch
1059 // ended this fetch block.
1060 bool predicted_branch = false;
1061
1062 while (offset < cacheBlkSize &&
1063 numInst < fetchWidth &&
1064 !predicted_branch) {
1065
1107 // If we're branching after this instruction, quite fetching
1108 // from the same block then.
1109 predicted_branch =
1110 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
1111 if (predicted_branch) {
1112 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
1113 fetch_PC, fetch_NPC);
1114 }
1115
1116 // Make sure this is a valid index.
1117 assert(offset <= cacheBlkSize - instSize);
1118
1119 if (!macroop) {
1120 // Get the instruction from the array of the cache line.
1121 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1122 (&cacheData[tid][offset]));
1123
1124 predecoder.setTC(cpu->thread[tid]->getTC());
1066 // Make sure this is a valid index.
1067 assert(offset <= cacheBlkSize - instSize);
1068
1069 if (!macroop) {
1070 // Get the instruction from the array of the cache line.
1071 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1072 (&cacheData[tid][offset]));
1073
1074 predecoder.setTC(cpu->thread[tid]->getTC());
1125 predecoder.moreBytes(fetch_PC, fetch_PC, inst);
1075 predecoder.moreBytes(fetchPC, fetchPC.instAddr(), inst);
1126
1076
1127 ext_inst = predecoder.getExtMachInst();
1128 staticInst = StaticInstPtr(ext_inst, fetch_PC);
1077 ext_inst = predecoder.getExtMachInst(fetchPC);
1078 staticInst = StaticInstPtr(ext_inst, fetchPC.instAddr());
1129 if (staticInst->isMacroop())
1130 macroop = staticInst;
1131 }
1132 do {
1133 if (macroop) {
1079 if (staticInst->isMacroop())
1080 macroop = staticInst;
1081 }
1082 do {
1083 if (macroop) {
1134 staticInst = macroop->fetchMicroop(fetch_MicroPC);
1084 staticInst = macroop->fetchMicroop(fetchPC.microPC());
1135 if (staticInst->isLastMicroop())
1136 macroop = NULL;
1137 }
1138
1139 // Get a sequence number.
1140 inst_seq = cpu->getAndIncrementInstSeq();
1141
1142 // Create a new DynInst from the instruction fetched.
1143 DynInstPtr instruction = new DynInst(staticInst,
1085 if (staticInst->isLastMicroop())
1086 macroop = NULL;
1087 }
1088
1089 // Get a sequence number.
1090 inst_seq = cpu->getAndIncrementInstSeq();
1091
1092 // Create a new DynInst from the instruction fetched.
1093 DynInstPtr instruction = new DynInst(staticInst,
1144 fetch_PC, fetch_NPC, fetch_MicroPC,
1145 next_PC, next_NPC, next_MicroPC,
1094 fetchPC, nextPC,
1146 inst_seq, cpu);
1147 instruction->setTid(tid);
1148
1149 instruction->setASID(tid);
1150
1151 instruction->setThreadState(cpu->thread[tid]);
1152
1095 inst_seq, cpu);
1096 instruction->setTid(tid);
1097
1098 instruction->setASID(tid);
1099
1100 instruction->setThreadState(cpu->thread[tid]);
1101
1153 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1154 "[sn:%lli]\n", tid, instruction->readPC(),
1155 instruction->readMicroPC(), inst_seq);
1102 DPRINTF(Fetch, "[tid:%i]: Instruction PC %s (%d) created "
1103 "[sn:%lli]\n", tid, instruction->pcState(),
1104 instruction->microPC(), inst_seq);
1156
1157 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1158
1105
1106 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1107
1159 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1160 tid, instruction->staticInst->disassemble(fetch_PC));
1108 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
1109 instruction->staticInst->
1110 disassemble(fetchPC.instAddr()));
1161
1162#if TRACING_ON
1163 instruction->traceData =
1164 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
1111
1112#if TRACING_ON
1113 instruction->traceData =
1114 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
1165 instruction->staticInst, instruction->readPC(),
1166 macroop, instruction->readMicroPC());
1115 instruction->staticInst, fetchPC, macroop);
1167#else
1168 instruction->traceData = NULL;
1169#endif
1170
1116#else
1117 instruction->traceData = NULL;
1118#endif
1119
1171 ///FIXME This needs to be more robust in dealing with delay slots
1120 // If we're branching after this instruction, quite fetching
1121 // from the same block then.
1122 predicted_branch = fetchPC.branching();
1172 predicted_branch |=
1123 predicted_branch |=
1173 lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
1124 lookupAndUpdateNextPC(instruction, nextPC);
1125 if (predicted_branch) {
1126 DPRINTF(Fetch, "Branch detected with PC = %s\n", fetchPC);
1127 }
1174
1175 // Add instruction to the CPU's list of instructions.
1176 instruction->setInstListIt(cpu->addInst(instruction));
1177
1178 // Write the instruction to the first slot in the queue
1179 // that heads to decode.
1180 toDecode->insts[numInst] = instruction;
1181
1182 toDecode->size++;
1183
1184 // Increment stat of fetched instructions.
1185 ++fetchedInsts;
1186
1187 // Move to the next instruction, unless we have a branch.
1128
1129 // Add instruction to the CPU's list of instructions.
1130 instruction->setInstListIt(cpu->addInst(instruction));
1131
1132 // Write the instruction to the first slot in the queue
1133 // that heads to decode.
1134 toDecode->insts[numInst] = instruction;
1135
1136 toDecode->size++;
1137
1138 // Increment stat of fetched instructions.
1139 ++fetchedInsts;
1140
1141 // Move to the next instruction, unless we have a branch.
1188 fetch_PC = next_PC;
1189 fetch_NPC = next_NPC;
1190 fetch_MicroPC = next_MicroPC;
1142 fetchPC = nextPC;
1191
1192 if (instruction->isQuiesce()) {
1193 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1194 curTick);
1195 fetchStatus[tid] = QuiescePending;
1196 ++numInst;
1197 status_change = true;
1198 break;
1199 }
1200
1201 ++numInst;
1202 } while (staticInst->isMicroop() &&
1203 !staticInst->isLastMicroop() &&
1204 numInst < fetchWidth);
1143
1144 if (instruction->isQuiesce()) {
1145 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1146 curTick);
1147 fetchStatus[tid] = QuiescePending;
1148 ++numInst;
1149 status_change = true;
1150 break;
1151 }
1152
1153 ++numInst;
1154 } while (staticInst->isMicroop() &&
1155 !staticInst->isLastMicroop() &&
1156 numInst < fetchWidth);
1205 offset += instSize;
1157 //XXX Masking out pal mode bit.
1158 offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid];
1206 }
1207
1208 if (predicted_branch) {
1209 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1210 "instruction encountered.\n", tid);
1211 } else if (numInst >= fetchWidth) {
1212 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1213 "for this cycle.\n", tid);

--- 5 unchanged lines hidden (view full) ---

1219
1220 if (numInst > 0) {
1221 wroteToTimeBuffer = true;
1222 }
1223
1224 // Now that fetching is completed, update the PC to signify what the next
1225 // cycle will be.
1226 if (fault == NoFault) {
1159 }
1160
1161 if (predicted_branch) {
1162 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1163 "instruction encountered.\n", tid);
1164 } else if (numInst >= fetchWidth) {
1165 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1166 "for this cycle.\n", tid);

--- 5 unchanged lines hidden (view full) ---

1172
1173 if (numInst > 0) {
1174 wroteToTimeBuffer = true;
1175 }
1176
1177 // Now that fetching is completed, update the PC to signify what the next
1178 // cycle will be.
1179 if (fault == NoFault) {
1227 PC[tid] = next_PC;
1228 nextPC[tid] = next_NPC;
1229 microPC[tid] = next_MicroPC;
1230 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1180 pc[tid] = nextPC;
1181 DPRINTF(Fetch, "[tid:%i]: Setting PC to %s.\n", tid, nextPC);
1231 } else {
1232 // We shouldn't be in an icache miss and also have a fault (an ITB
1233 // miss)
1234 if (fetchStatus[tid] == IcacheWaitResponse) {
1235 panic("Fetch should have exited prior to this!");
1236 }
1237
1238 // Send the fault to commit. This thread will not do anything
1239 // until commit handles the fault. The only other way it can
1240 // wake up is if a squash comes along and changes the PC.
1241 assert(numInst < fetchWidth);
1242 // Get a sequence number.
1243 inst_seq = cpu->getAndIncrementInstSeq();
1244 // We will use a nop in order to carry the fault.
1245 ext_inst = TheISA::NoopMachInst;
1246
1247 // Create a new DynInst from the dummy nop.
1182 } else {
1183 // We shouldn't be in an icache miss and also have a fault (an ITB
1184 // miss)
1185 if (fetchStatus[tid] == IcacheWaitResponse) {
1186 panic("Fetch should have exited prior to this!");
1187 }
1188
1189 // Send the fault to commit. This thread will not do anything
1190 // until commit handles the fault. The only other way it can
1191 // wake up is if a squash comes along and changes the PC.
1192 assert(numInst < fetchWidth);
1193 // Get a sequence number.
1194 inst_seq = cpu->getAndIncrementInstSeq();
1195 // We will use a nop in order to carry the fault.
1196 ext_inst = TheISA::NoopMachInst;
1197
1198 // Create a new DynInst from the dummy nop.
1248 DynInstPtr instruction = new DynInst(ext_inst,
1249 fetch_PC, fetch_NPC, fetch_MicroPC,
1250 next_PC, next_NPC, next_MicroPC,
1199 DynInstPtr instruction = new DynInst(ext_inst, fetchPC, nextPC,
1251 inst_seq, cpu);
1200 inst_seq, cpu);
1252 instruction->setPredTarg(next_NPC, next_NPC + instSize, 0);
1201 TheISA::advancePC(nextPC, instruction->staticInst);
1202 instruction->setPredTarg(nextPC);
1253 instruction->setTid(tid);
1254
1255 instruction->setASID(tid);
1256
1257 instruction->setThreadState(cpu->thread[tid]);
1258
1259 instruction->traceData = NULL;
1260

--- 6 unchanged lines hidden (view full) ---

1267
1268 wroteToTimeBuffer = true;
1269
1270 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1271
1272 fetchStatus[tid] = TrapPending;
1273 status_change = true;
1274
1203 instruction->setTid(tid);
1204
1205 instruction->setASID(tid);
1206
1207 instruction->setThreadState(cpu->thread[tid]);
1208
1209 instruction->traceData = NULL;
1210

--- 6 unchanged lines hidden (view full) ---

1217
1218 wroteToTimeBuffer = true;
1219
1220 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1221
1222 fetchStatus[tid] = TrapPending;
1223 status_change = true;
1224
1275 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1276 tid, fault->name(), PC[tid]);
1225 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s",
1226 tid, fault->name(), pc[tid]);
1277 }
1278}
1279
1280template<class Impl>
1281void
1282DefaultFetch<Impl>::recvRetry()
1283{
1284 if (retryPkt != NULL) {

--- 169 unchanged lines hidden --- 		1227 }
1228}
1229
1230template<class Impl>
1231void
1232DefaultFetch<Impl>::recvRetry()
1233{
1234 if (retryPkt != NULL) {

--- 169 unchanged lines hidden ---