fetch_impl.hh (6221:58a3c04e6344) fetch_impl.hh (6429:7ed8937e375a)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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591 // If we've already got the block, no need to try to fetch it again.
592 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
593 return true;
594 }
595
596 // Setup the memReq to do a read of the first instruction's address.
597 // Set the appropriate read size and flags as well.
598 // Build request here.
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 582 unchanged lines hidden (view full) ---

591 // If we've already got the block, no need to try to fetch it again.
592 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
593 return true;
594 }
595
596 // Setup the memReq to do a read of the first instruction's address.
597 // Set the appropriate read size and flags as well.
598 // Build request here.
599 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
600 fetch_PC, cpu->thread[tid]->contextId(),
601 tid);
599 RequestPtr mem_req =
600 new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
601 fetch_PC, cpu->thread[tid]->contextId(), tid);
602
603 memReq[tid] = mem_req;
604
605 // Translate the instruction request.
606 fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
607 BaseTLB::Execute);
608
609 // In the case of faults, the fetch stage may need to stall and wait

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603 memReq[tid] = mem_req;
604
605 // Translate the instruction request.
606 fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
607 BaseTLB::Execute);
608
609 // In the case of faults, the fetch stage may need to stall and wait

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