fetch_impl.hh (5712:199d31b47f7b) fetch_impl.hh (5714:76abee886def)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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357 cacheDataValid[tid] = false;
358 }
359}
360
361template<class Impl>
362void
363DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
364{
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 348 unchanged lines hidden (view full) ---

357 cacheDataValid[tid] = false;
358 }
359}
360
361template<class Impl>
362void
363DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
364{
365 unsigned tid = pkt->req->getThreadNum();
365 unsigned tid = pkt->req->threadId();
366
367 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
368
369 assert(!pkt->wasNacked());
370
371 // Only change the status if it's still waiting on the icache access
372 // to return.
373 if (fetchStatus[tid] != IcacheWaitResponse ||

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588 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
589 return true;
590 }
591
592 // Setup the memReq to do a read of the first instruction's address.
593 // Set the appropriate read size and flags as well.
594 // Build request here.
595 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
366
367 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
368
369 assert(!pkt->wasNacked());
370
371 // Only change the status if it's still waiting on the icache access
372 // to return.
373 if (fetchStatus[tid] != IcacheWaitResponse ||

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588 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
589 return true;
590 }
591
592 // Setup the memReq to do a read of the first instruction's address.
593 // Set the appropriate read size and flags as well.
594 // Build request here.
595 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
596 fetch_PC, cpu->cpuId(), tid);
596 fetch_PC, cpu->thread[tid]->contextId(),
597 tid);
597
598 memReq[tid] = mem_req;
599
600 // Translate the instruction request.
601 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
602
603 // In the case of faults, the fetch stage may need to stall and wait
604 // for the ITB miss to be handled.

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599 memReq[tid] = mem_req;
600
601 // Translate the instruction request.
602 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
603
604 // In the case of faults, the fetch stage may need to stall and wait
605 // for the ITB miss to be handled.

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