| fetch_impl.hh (5529:9ae69b9cd7fd) | fetch_impl.hh (5712:199d31b47f7b) |
|---|---|
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 579 unchanged lines hidden (view full) --- 588 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { 589 return true; 590 } 591 592 // Setup the memReq to do a read of the first instruction's address. 593 // Set the appropriate read size and flags as well. 594 // Build request here. 595 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 579 unchanged lines hidden (view full) --- 588 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { 589 return true; 590 } 591 592 // Setup the memReq to do a read of the first instruction's address. 593 // Set the appropriate read size and flags as well. 594 // Build request here. 595 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, |
| 596 fetch_PC, cpu->readCpuId(), tid); | 596 fetch_PC, cpu->cpuId(), tid); |
| 597 598 memReq[tid] = mem_req; 599 600 // Translate the instruction request. 601 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]); 602 603 // In the case of faults, the fetch stage may need to stall and wait 604 // for the ITB miss to be handled. --- 838 unchanged lines hidden --- | 597 598 memReq[tid] = mem_req; 599 600 // Translate the instruction request. 601 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]); 602 603 // In the case of faults, the fetch stage may need to stall and wait 604 // for the ITB miss to be handled. --- 838 unchanged lines hidden --- |