| fetch_impl.hh (4991:7e3bb2eabbbf) | fetch_impl.hh (4997:e7380529bd2d) |
|---|---|
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 1212 unchanged lines hidden (view full) --- 1221 // miss) 1222 if (fetchStatus[tid] == IcacheWaitResponse) { 1223 panic("Fetch should have exited prior to this!"); 1224 } 1225 1226 // Send the fault to commit. This thread will not do anything 1227 // until commit handles the fault. The only other way it can 1228 // wake up is if a squash comes along and changes the PC. | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 1212 unchanged lines hidden (view full) --- 1221 // miss) 1222 if (fetchStatus[tid] == IcacheWaitResponse) { 1223 panic("Fetch should have exited prior to this!"); 1224 } 1225 1226 // Send the fault to commit. This thread will not do anything 1227 // until commit handles the fault. The only other way it can 1228 // wake up is if a squash comes along and changes the PC. |
| 1229#if FULL_SYSTEM | |
| 1230 assert(numInst < fetchWidth); 1231 // Get a sequence number. 1232 inst_seq = cpu->getAndIncrementInstSeq(); 1233 // We will use a nop in order to carry the fault. 1234 ext_inst = TheISA::NoopMachInst; 1235 1236 // Create a new DynInst from the dummy nop. 1237 DynInstPtr instruction = new DynInst(ext_inst, --- 15 unchanged lines hidden (view full) --- 1253 1254 toDecode->insts[numInst] = instruction; 1255 toDecode->size++; 1256 1257 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1258 1259 fetchStatus[tid] = TrapPending; 1260 status_change = true; | 1229 assert(numInst < fetchWidth); 1230 // Get a sequence number. 1231 inst_seq = cpu->getAndIncrementInstSeq(); 1232 // We will use a nop in order to carry the fault. 1233 ext_inst = TheISA::NoopMachInst; 1234 1235 // Create a new DynInst from the dummy nop. 1236 DynInstPtr instruction = new DynInst(ext_inst, --- 15 unchanged lines hidden (view full) --- 1252 1253 toDecode->insts[numInst] = instruction; 1254 toDecode->size++; 1255 1256 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1257 1258 fetchStatus[tid] = TrapPending; 1259 status_change = true; |
| 1261#else // !FULL_SYSTEM 1262 fetchStatus[tid] = TrapPending; 1263 status_change = true; | |
| 1264 | 1260 |
| 1265#endif // FULL_SYSTEM | |
| 1266 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", 1267 tid, fault->name(), PC[tid]); 1268 } 1269} 1270 1271template<class Impl> 1272void 1273DefaultFetch<Impl>::recvRetry() --- 170 unchanged lines hidden --- | 1261 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", 1262 tid, fault->name(), PC[tid]); 1263 } 1264} 1265 1266template<class Impl> 1267void 1268DefaultFetch<Impl>::recvRetry() --- 170 unchanged lines hidden --- |