fetch_impl.hh (4593:16b19397172c) fetch_impl.hh (4632:be5b8f67b8fb)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 15 unchanged lines hidden (view full) ---

24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 15 unchanged lines hidden (view full) ---

24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <algorithm>
33#include <cstring>
34
35#include "config/use_checker.hh"
36
37#include "arch/isa_traits.hh"
38#include "arch/utility.hh"
39#include "cpu/checker/cpu.hh"
40#include "cpu/exetrace.hh"
41#include "cpu/o3/fetch.hh"
42#include "mem/packet.hh"
43#include "mem/request.hh"
44#include "sim/byteswap.hh"
45#include "sim/host.hh"
46#include "sim/core.hh"
47
48#if FULL_SYSTEM
49#include "arch/tlb.hh"
50#include "arch/vtophys.hh"
51#include "sim/system.hh"
52#endif // FULL_SYSTEM
53
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/core.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "sim/system.hh"
49#endif // FULL_SYSTEM
50
51#include <algorithm>
52
54template<class Impl>
55void
56DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
57{
58 Port::setPeer(port);
59
60 fetch->setIcache();
61}

--- 308 unchanged lines hidden (view full) ---

370 pkt->req != memReq[tid] ||
371 isSwitchedOut()) {
372 ++fetchIcacheSquashes;
373 delete pkt->req;
374 delete pkt;
375 return;
376 }
377
53template<class Impl>
54void
55DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
56{
57 Port::setPeer(port);
58
59 fetch->setIcache();
60}

--- 308 unchanged lines hidden (view full) ---

369 pkt->req != memReq[tid] ||
370 isSwitchedOut()) {
371 ++fetchIcacheSquashes;
372 delete pkt->req;
373 delete pkt;
374 return;
375 }
376
378 memcpy(cacheData[tid], pkt->getPtr(), cacheBlkSize);
377 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
379 cacheDataValid[tid] = true;
380
381 if (!drainPending) {
382 // Wake up the CPU (if it went to sleep and was waiting on
383 // this completion event).
384 cpu->wakeCPU();
385
386 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",

--- 383 unchanged lines hidden (view full) ---

770 }
771
772 return Inactive;
773}
774
775template <class Impl>
776void
777DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
378 cacheDataValid[tid] = true;
379
380 if (!drainPending) {
381 // Wake up the CPU (if it went to sleep and was waiting on
382 // this completion event).
383 cpu->wakeCPU();
384
385 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",

--- 383 unchanged lines hidden (view full) ---

769 }
770
771 return Inactive;
772}
773
774template <class Impl>
775void
776DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
778 const InstSeqNum &seq_num,
779 bool squash_delay_slot, unsigned tid)
777 const InstSeqNum &seq_num, unsigned tid)
780{
781 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
782
783 doSquash(new_PC, new_NPC, tid);
784
778{
779 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
780
781 doSquash(new_PC, new_NPC, tid);
782
785#if ISA_HAS_DELAY_SLOT
786 // Tell the CPU to remove any instructions that are not in the ROB.
783 // Tell the CPU to remove any instructions that are not in the ROB.
787 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
788#else
789 // Tell the CPU to remove any instructions that are not in the ROB.
790 cpu->removeInstsNotInROB(tid, true, 0);
791#endif
784 cpu->removeInstsNotInROB(tid);
792}
793
794template <class Impl>
795void
796DefaultFetch<Impl>::tick()
797{
798 std::list<unsigned>::iterator threads = activeThreads->begin();
799 std::list<unsigned>::iterator end = activeThreads->end();

--- 92 unchanged lines hidden (view full) ---

892 stalls[tid].commit = false;
893 }
894
895 // Check squash signals from commit.
896 if (fromCommit->commitInfo[tid].squash) {
897
898 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
899 "from commit.\n",tid);
785}
786
787template <class Impl>
788void
789DefaultFetch<Impl>::tick()
790{
791 std::list<unsigned>::iterator threads = activeThreads->begin();
792 std::list<unsigned>::iterator end = activeThreads->end();

--- 92 unchanged lines hidden (view full) ---

885 stalls[tid].commit = false;
886 }
887
888 // Check squash signals from commit.
889 if (fromCommit->commitInfo[tid].squash) {
890
891 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
892 "from commit.\n",tid);
900
901#if ISA_HAS_DELAY_SLOT
902 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
903#else
904 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
905#endif
906 // In any case, squash.
907 squash(fromCommit->commitInfo[tid].nextPC,
908 fromCommit->commitInfo[tid].nextNPC,
893 // In any case, squash.
894 squash(fromCommit->commitInfo[tid].nextPC,
895 fromCommit->commitInfo[tid].nextNPC,
909 doneSeqNum,
910 fromCommit->commitInfo[tid].squashDelaySlot,
896 fromCommit->commitInfo[tid].doneSeqNum,
911 tid);
912
913 // Also check if there's a mispredict that happened.
914 if (fromCommit->commitInfo[tid].branchMispredict) {
915 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
916 fromCommit->commitInfo[tid].nextPC,
917 fromCommit->commitInfo[tid].branchTaken,
918 tid);

--- 32 unchanged lines hidden (view full) ---

951 tid);
952 } else {
953 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
954 tid);
955 }
956
957 if (fetchStatus[tid] != Squashing) {
958
897 tid);
898
899 // Also check if there's a mispredict that happened.
900 if (fromCommit->commitInfo[tid].branchMispredict) {
901 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
902 fromCommit->commitInfo[tid].nextPC,
903 fromCommit->commitInfo[tid].branchTaken,
904 tid);

--- 32 unchanged lines hidden (view full) ---

937 tid);
938 } else {
939 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
940 tid);
941 }
942
943 if (fetchStatus[tid] != Squashing) {
944
959#if ISA_HAS_DELAY_SLOT
960 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
961#else
962 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
963#endif
964 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
965 fromDecode->decodeInfo[tid].nextPC,
966 fromDecode->decodeInfo[tid].nextNPC);
967 // Squash unless we're already squashing
968 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
969 fromDecode->decodeInfo[tid].nextNPC,
945 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
946 fromDecode->decodeInfo[tid].nextPC,
947 fromDecode->decodeInfo[tid].nextNPC);
948 // Squash unless we're already squashing
949 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
950 fromDecode->decodeInfo[tid].nextNPC,
970 doneSeqNum,
951 fromDecode->decodeInfo[tid].doneSeqNum,
971 tid);
972
973 return true;
974 }
975 }
976
977 if (checkStall(tid) &&
978 fetchStatus[tid] != IcacheWaitResponse &&

--- 144 unchanged lines hidden (view full) ---

1123 // Make sure this is a valid index.
1124 assert(offset <= cacheBlkSize - instSize);
1125
1126 // Get the instruction from the array of the cache line.
1127 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1128 (&cacheData[tid][offset]));
1129
1130 predecoder.setTC(cpu->thread[tid]->getTC());
952 tid);
953
954 return true;
955 }
956 }
957
958 if (checkStall(tid) &&
959 fetchStatus[tid] != IcacheWaitResponse &&

--- 144 unchanged lines hidden (view full) ---

1104 // Make sure this is a valid index.
1105 assert(offset <= cacheBlkSize - instSize);
1106
1107 // Get the instruction from the array of the cache line.
1108 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1109 (&cacheData[tid][offset]));
1110
1111 predecoder.setTC(cpu->thread[tid]->getTC());
1131 predecoder.moreBytes(fetch_PC, fetch_PC, inst);
1112 predecoder.moreBytes(fetch_PC, 0, inst);
1132
1133 ext_inst = predecoder.getExtMachInst();
1134
1135 // Create a new DynInst from the instruction fetched.
1136 DynInstPtr instruction = new DynInst(ext_inst,
1137 fetch_PC, fetch_NPC,
1138 next_PC, next_NPC,
1139 inst_seq, cpu);

--- 7 unchanged lines hidden (view full) ---

1147 "[sn:%lli]\n",
1148 tid, instruction->readPC(), inst_seq);
1149
1150 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1151
1152 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1153 tid, instruction->staticInst->disassemble(fetch_PC));
1154
1113
1114 ext_inst = predecoder.getExtMachInst();
1115
1116 // Create a new DynInst from the instruction fetched.
1117 DynInstPtr instruction = new DynInst(ext_inst,
1118 fetch_PC, fetch_NPC,
1119 next_PC, next_NPC,
1120 inst_seq, cpu);

--- 7 unchanged lines hidden (view full) ---

1128 "[sn:%lli]\n",
1129 tid, instruction->readPC(), inst_seq);
1130
1131 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1132
1133 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1134 tid, instruction->staticInst->disassemble(fetch_PC));
1135
1155#if TRACING_ON
1156 instruction->traceData =
1157 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1158 instruction->staticInst,
1159 instruction->readPC());
1136 instruction->traceData =
1137 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1138 instruction->staticInst,
1139 instruction->readPC());
1160#else
1161 instruction->traceData = NULL;
1162#endif
1163
1164 ///FIXME This needs to be more robust in dealing with delay slots
1140
1141 ///FIXME This needs to be more robust in dealing with delay slots
1165#if !ISA_HAS_DELAY_SLOT
1166// predicted_branch |=
1167#endif
1168 lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
1169 predicted_branch |= (next_PC != fetch_NPC);
1170
1171 // Add instruction to the CPU's list of instructions.
1172 instruction->setInstListIt(cpu->addInst(instruction));
1173
1174 // Write the instruction to the first slot in the queue
1175 // that heads to decode.

--- 37 unchanged lines hidden (view full) ---

1213 }
1214
1215 // Now that fetching is completed, update the PC to signify what the next
1216 // cycle will be.
1217 if (fault == NoFault) {
1218 PC[tid] = next_PC;
1219 nextPC[tid] = next_NPC;
1220 nextNPC[tid] = next_NPC + instSize;
1142 lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
1143 predicted_branch |= (next_PC != fetch_NPC);
1144
1145 // Add instruction to the CPU's list of instructions.
1146 instruction->setInstListIt(cpu->addInst(instruction));
1147
1148 // Write the instruction to the first slot in the queue
1149 // that heads to decode.

--- 37 unchanged lines hidden (view full) ---

1187 }
1188
1189 // Now that fetching is completed, update the PC to signify what the next
1190 // cycle will be.
1191 if (fault == NoFault) {
1192 PC[tid] = next_PC;
1193 nextPC[tid] = next_NPC;
1194 nextNPC[tid] = next_NPC + instSize;
1221#if ISA_HAS_DELAY_SLOT
1222 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1223#else
1224 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1195 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1225#endif
1226 } else {
1227 // We shouldn't be in an icache miss and also have a fault (an ITB
1228 // miss)
1229 if (fetchStatus[tid] == IcacheWaitResponse) {
1230 panic("Fetch should have exited prior to this!");
1231 }
1232
1233 // Send the fault to commit. This thread will not do anything

--- 217 unchanged lines hidden --- 		1196 } else {
1197 // We shouldn't be in an icache miss and also have a fault (an ITB
1198 // miss)
1199 if (fetchStatus[tid] == IcacheWaitResponse) {
1200 panic("Fetch should have exited prior to this!");
1201 }
1202
1203 // Send the fault to commit. This thread will not do anything

--- 217 unchanged lines hidden ---