fetch_impl.hh (4318:eb4241362a80) fetch_impl.hh (4329:52057dbec096)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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105template<class Impl>
106void
107DefaultFetch<Impl>::IcachePort::recvRetry()
108{
109 fetch->recvRetry();
110}
111
112template<class Impl>
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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105template<class Impl>
106void
107DefaultFetch<Impl>::IcachePort::recvRetry()
108{
109 fetch->recvRetry();
110}
111
112template<class Impl>
113DefaultFetch::DefaultFetch(Params *params)
114 : branchPred(params),
113DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
114 : cpu(_cpu),
115 branchPred(params),
115 predecoder(NULL),
116 decodeToFetchDelay(params->decodeToFetchDelay),
117 renameToFetchDelay(params->renameToFetchDelay),
118 iewToFetchDelay(params->iewToFetchDelay),
119 commitToFetchDelay(params->commitToFetchDelay),
120 fetchWidth(params->fetchWidth),
121 cacheBlocked(false),
122 retryPkt(NULL),

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158 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
159 } else {
160 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
161 " RoundRobin,LSQcount,IQcount}\n");
162 }
163
164 // Get the size of an instruction.
165 instSize = sizeof(TheISA::MachInst);
116 predecoder(NULL),
117 decodeToFetchDelay(params->decodeToFetchDelay),
118 renameToFetchDelay(params->renameToFetchDelay),
119 iewToFetchDelay(params->iewToFetchDelay),
120 commitToFetchDelay(params->commitToFetchDelay),
121 fetchWidth(params->fetchWidth),
122 cacheBlocked(false),
123 retryPkt(NULL),

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159 DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
160 } else {
161 fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
162 " RoundRobin,LSQcount,IQcount}\n");
163 }
164
165 // Get the size of an instruction.
166 instSize = sizeof(TheISA::MachInst);
167
168 // Name is finally available, so create the port.
169 icachePort = new IcachePort(this);
170
171 icachePort->snoopRangeSent = false;
172
173#if USE_CHECKER
174 if (cpu->checker) {
175 cpu->checker->setIcachePort(icachePort);
176 }
177#endif
166}
167
168template <class Impl>
169std::string
170DefaultFetch<Impl>::name() const
171{
172 return cpu->name() + ".fetch";
173}

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259 .flags(Stats::total);
260 fetchRate = fetchedInsts / cpu->numCycles;
261
262 branchPred.regStats();
263}
264
265template<class Impl>
266void
178}
179
180template <class Impl>
181std::string
182DefaultFetch<Impl>::name() const
183{
184 return cpu->name() + ".fetch";
185}

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271 .flags(Stats::total);
272 fetchRate = fetchedInsts / cpu->numCycles;
273
274 branchPred.regStats();
275}
276
277template<class Impl>
278void
267DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
268{
269 cpu = cpu_ptr;
270 DPRINTF(Fetch, "Setting the CPU pointer.\n");
271
272 // Name is finally available, so create the port.
273 icachePort = new IcachePort(this);
274
275 icachePort->snoopRangeSent = false;
276
277#if USE_CHECKER
278 if (cpu->checker) {
279 cpu->checker->setIcachePort(icachePort);
280 }
281#endif
282
283 // Schedule fetch to get the correct PC from the CPU
284 // scheduleFetchStartupEvent(1);
285
286 // Fetch needs to start fetching instructions at the very beginning,
287 // so it must start up in active state.
288 switchToActive();
289}
290
291template<class Impl>
292void
293DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
294{
295 timeBuffer = time_buffer;
296
297 // Create wires to get information from proper places in time buffer.
298 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
299 fromRename = timeBuffer->getWire(-renameToFetchDelay);
300 fromIEW = timeBuffer->getWire(-iewToFetchDelay);

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337
338 memReq[tid] = NULL;
339
340 stalls[tid].decode = false;
341 stalls[tid].rename = false;
342 stalls[tid].iew = false;
343 stalls[tid].commit = false;
344 }
279DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
280{
281 timeBuffer = time_buffer;
282
283 // Create wires to get information from proper places in time buffer.
284 fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
285 fromRename = timeBuffer->getWire(-renameToFetchDelay);
286 fromIEW = timeBuffer->getWire(-iewToFetchDelay);

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323
324 memReq[tid] = NULL;
325
326 stalls[tid].decode = false;
327 stalls[tid].rename = false;
328 stalls[tid].iew = false;
329 stalls[tid].commit = false;
330 }
331
332 // Schedule fetch to get the correct PC from the CPU
333 // scheduleFetchStartupEvent(1);
334
335 // Fetch needs to start fetching instructions at the very beginning,
336 // so it must start up in active state.
337 switchToActive();
345}
346
347template<class Impl>
348void
349DefaultFetch<Impl>::setIcache()
350{
351 // Size of cache block.
352 cacheBlkSize = icachePort->peerBlockSize();

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339
340template<class Impl>
341void
342DefaultFetch<Impl>::setIcache()
343{
344 // Size of cache block.
345 cacheBlkSize = icachePort->peerBlockSize();

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