fetch_impl.hh (4284:c8800319ed0c) fetch_impl.hh (4302:c45514c856b0)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "sim/system.hh"
49#endif // FULL_SYSTEM
50
51#include <algorithm>
52
53template<class Impl>
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "sim/system.hh"
49#endif // FULL_SYSTEM
50
51#include <algorithm>
52
53template<class Impl>
54void
55DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
56{
57 Port::setPeer(port);
58
59 fetch->setIcache();
60}
61
62template<class Impl>
54Tick
55DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
56{
57 panic("DefaultFetch doesn't expect recvAtomic callback!");
58 return curTick;
59}
60
61template<class Impl>

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318{
319 // Setup PC and nextPC with initial state.
320 for (int tid = 0; tid < numThreads; tid++) {
321 PC[tid] = cpu->readPC(tid);
322 nextPC[tid] = cpu->readNextPC(tid);
323 nextNPC[tid] = cpu->readNextNPC(tid);
324 }
325
63Tick
64DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
65{
66 panic("DefaultFetch doesn't expect recvAtomic callback!");
67 return curTick;
68}
69
70template<class Impl>

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327{
328 // Setup PC and nextPC with initial state.
329 for (int tid = 0; tid < numThreads; tid++) {
330 PC[tid] = cpu->readPC(tid);
331 nextPC[tid] = cpu->readNextPC(tid);
332 nextNPC[tid] = cpu->readNextNPC(tid);
333 }
334
326 // Size of cache block.
327 cacheBlkSize = icachePort->peerBlockSize();
328
329 // Create mask to get rid of offset bits.
330 cacheBlkMask = (cacheBlkSize - 1);
331
332 for (int tid=0; tid < numThreads; tid++) {
333
334 fetchStatus[tid] = Running;
335
336 priorityList.push_back(tid);
337
338 memReq[tid] = NULL;
339
335 for (int tid=0; tid < numThreads; tid++) {
336
337 fetchStatus[tid] = Running;
338
339 priorityList.push_back(tid);
340
341 memReq[tid] = NULL;
342
340 // Create space to store a cache line.
341 cacheData[tid] = new uint8_t[cacheBlkSize];
342 cacheDataPC[tid] = 0;
343 cacheDataValid[tid] = false;
344
345 stalls[tid].decode = false;
346 stalls[tid].rename = false;
347 stalls[tid].iew = false;
348 stalls[tid].commit = false;
349 }
350}
351
352template<class Impl>
353void
343 stalls[tid].decode = false;
344 stalls[tid].rename = false;
345 stalls[tid].iew = false;
346 stalls[tid].commit = false;
347 }
348}
349
350template<class Impl>
351void
352DefaultFetch<Impl>::setIcache()
353{
354 // Size of cache block.
355 cacheBlkSize = icachePort->peerBlockSize();
356
357 // Create mask to get rid of offset bits.
358 cacheBlkMask = (cacheBlkSize - 1);
359
360 for (int tid=0; tid < numThreads; tid++) {
361 // Create space to store a cache line.
362 cacheData[tid] = new uint8_t[cacheBlkSize];
363 cacheDataPC[tid] = 0;
364 cacheDataValid[tid] = false;
365 }
366}
367
368template<class Impl>
369void
354DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
355{
356 unsigned tid = pkt->req->getThreadNum();
357
358 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
359
360 // Only change the status if it's still waiting on the icache access
361 // to return.

--- 1078 unchanged lines hidden --- 		370DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
371{
372 unsigned tid = pkt->req->getThreadNum();
373
374 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
375
376 // Only change the status if it's still waiting on the icache access
377 // to return.

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