fetch_impl.hh (4032:8b987a6a2afc) fetch_impl.hh (4167:ce5d0f62f13b)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
43#include "sim/core.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "sim/system.hh"
49#endif // FULL_SYSTEM
50
51#include <algorithm>

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597 memReq[tid]->paddr);
598 ret_fault = TheISA::genMachineCheckFault();
599 return false;
600 }
601#endif
602
603 // Build packet here.
604 PacketPtr data_pkt = new Packet(mem_req,
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "sim/system.hh"
49#endif // FULL_SYSTEM
50
51#include <algorithm>

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597 memReq[tid]->paddr);
598 ret_fault = TheISA::genMachineCheckFault();
599 return false;
600 }
601#endif
602
603 // Build packet here.
604 PacketPtr data_pkt = new Packet(mem_req,
605 Packet::ReadReq, Packet::Broadcast);
605 MemCmd::ReadReq, Packet::Broadcast);
606 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
607
608 cacheDataPC[tid] = block_PC;
609 cacheDataValid[tid] = false;
610
611 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
612
613 fetchedCacheLines++;
614
615 // Now do the timing access to see whether or not the instruction
616 // exists within the cache.
617 if (!icachePort->sendTiming(data_pkt)) {
618 if (data_pkt->result == Packet::BadAddress) {
619 fault = TheISA::genMachineCheckFault();
620 delete mem_req;
621 memReq[tid] = NULL;
606 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
607
608 cacheDataPC[tid] = block_PC;
609 cacheDataValid[tid] = false;
610
611 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
612
613 fetchedCacheLines++;
614
615 // Now do the timing access to see whether or not the instruction
616 // exists within the cache.
617 if (!icachePort->sendTiming(data_pkt)) {
618 if (data_pkt->result == Packet::BadAddress) {
619 fault = TheISA::genMachineCheckFault();
620 delete mem_req;
621 memReq[tid] = NULL;
622 warn("Bad address!\n");
623 }
624 assert(retryPkt == NULL);
625 assert(retryTid == -1);
626 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
627 fetchStatus[tid] = IcacheWaitRetry;
628 retryPkt = data_pkt;
629 retryTid = tid;
630 cacheBlocked = true;

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665 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
666 tid);
667 memReq[tid] = NULL;
668 }
669
670 // Get rid of the retrying packet if it was from this thread.
671 if (retryTid == tid) {
672 assert(cacheBlocked);
622 }
623 assert(retryPkt == NULL);
624 assert(retryTid == -1);
625 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
626 fetchStatus[tid] = IcacheWaitRetry;
627 retryPkt = data_pkt;
628 retryTid = tid;
629 cacheBlocked = true;

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664 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
665 tid);
666 memReq[tid] = NULL;
667 }
668
669 // Get rid of the retrying packet if it was from this thread.
670 if (retryTid == tid) {
671 assert(cacheBlocked);
673 if (retryPkt) {
674 delete retryPkt->req;
675 delete retryPkt;
676 }
677 retryPkt = NULL;
672 cacheBlocked = false;
678 retryTid = -1;
673 retryTid = -1;
674 delete retryPkt->req;
675 delete retryPkt;
676 retryPkt = NULL;
679 }
680
681 fetchStatus[tid] = Squashing;
682
683 ++fetchSquashCycles;
684}
685
686template<class Impl>

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1149
1150 instruction->traceData =
1151 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1152 instruction->staticInst,
1153 instruction->readPC());
1154
1155 ///FIXME This needs to be more robust in dealing with delay slots
1156#if !ISA_HAS_DELAY_SLOT
677 }
678
679 fetchStatus[tid] = Squashing;
680
681 ++fetchSquashCycles;
682}
683
684template<class Impl>

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1147
1148 instruction->traceData =
1149 Trace::getInstRecord(curTick, cpu->tcBase(tid),
1150 instruction->staticInst,
1151 instruction->readPC());
1152
1153 ///FIXME This needs to be more robust in dealing with delay slots
1154#if !ISA_HAS_DELAY_SLOT
1157// predicted_branch |=
1155 predicted_branch |=
1158#endif
1159 lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
1160 predicted_branch |= (next_PC != fetch_NPC);
1161
1162 // Add instruction to the CPU's list of instructions.
1163 instruction->setInstListIt(cpu->addInst(instruction));
1164
1165 // Write the instruction to the first slot in the queue

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1220 if (fetchStatus[tid] == IcacheWaitResponse) {
1221 panic("Fetch should have exited prior to this!");
1222 }
1223
1224 // Send the fault to commit. This thread will not do anything
1225 // until commit handles the fault. The only other way it can
1226 // wake up is if a squash comes along and changes the PC.
1227#if FULL_SYSTEM
1156#endif
1157 lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
1158 predicted_branch |= (next_PC != fetch_NPC);
1159
1160 // Add instruction to the CPU's list of instructions.
1161 instruction->setInstListIt(cpu->addInst(instruction));
1162
1163 // Write the instruction to the first slot in the queue

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1218 if (fetchStatus[tid] == IcacheWaitResponse) {
1219 panic("Fetch should have exited prior to this!");
1220 }
1221
1222 // Send the fault to commit. This thread will not do anything
1223 // until commit handles the fault. The only other way it can
1224 // wake up is if a squash comes along and changes the PC.
1225#if FULL_SYSTEM
1228 assert(numInst < fetchWidth);
1226 assert(numInst != fetchWidth);
1229 // Get a sequence number.
1230 inst_seq = cpu->getAndIncrementInstSeq();
1231 // We will use a nop in order to carry the fault.
1232 ext_inst = TheISA::NoopMachInst;
1233
1234 // Create a new DynInst from the dummy nop.
1235 DynInstPtr instruction = new DynInst(ext_inst,
1236 fetch_PC, fetch_NPC,

--- 205 unchanged lines hidden --- 		1227 // Get a sequence number.
1228 inst_seq = cpu->getAndIncrementInstSeq();
1229 // We will use a nop in order to carry the fault.
1230 ext_inst = TheISA::NoopMachInst;
1231
1232 // Create a new DynInst from the dummy nop.
1233 DynInstPtr instruction = new DynInst(ext_inst,
1234 fetch_PC, fetch_NPC,

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