fetch_impl.hh (3778:ac52cbef744c) | fetch_impl.hh (3791:f1783bae1afe) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 137 unchanged lines hidden (view full) --- 146 } else if (policy == "lsqcount") { 147 fetchPolicy = LSQ; 148 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 149 } else { 150 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 151 " RoundRobin,LSQcount,IQcount}\n"); 152 } 153 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 137 unchanged lines hidden (view full) --- 146 } else if (policy == "lsqcount") { 147 fetchPolicy = LSQ; 148 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 149 } else { 150 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 151 " RoundRobin,LSQcount,IQcount}\n"); 152 } 153 |
154 // Size of cache block. 155 cacheBlkSize = 64; 156 157 // Create mask to get rid of offset bits. 158 cacheBlkMask = (cacheBlkSize - 1); 159 160 for (int tid=0; tid < numThreads; tid++) { 161 162 fetchStatus[tid] = Running; 163 164 priorityList.push_back(tid); 165 166 memReq[tid] = NULL; 167 168 // Create space to store a cache line. 169 cacheData[tid] = new uint8_t[cacheBlkSize]; 170 cacheDataPC[tid] = 0; 171 cacheDataValid[tid] = false; 172 173 delaySlotInfo[tid].branchSeqNum = -1; 174 delaySlotInfo[tid].numInsts = 0; 175 delaySlotInfo[tid].targetAddr = 0; 176 delaySlotInfo[tid].targetReady = false; 177 178 stalls[tid].decode = false; 179 stalls[tid].rename = false; 180 stalls[tid].iew = false; 181 stalls[tid].commit = false; 182 } 183 | |
184 // Get the size of an instruction. 185 instSize = sizeof(TheISA::MachInst); 186} 187 188template <class Impl> 189std::string 190DefaultFetch<Impl>::name() const 191{ --- 156 unchanged lines hidden (view full) --- 348 // Setup PC and nextPC with initial state. 349 for (int tid = 0; tid < numThreads; tid++) { 350 PC[tid] = cpu->readPC(tid); 351 nextPC[tid] = cpu->readNextPC(tid); 352#if ISA_HAS_DELAY_SLOT 353 nextNPC[tid] = cpu->readNextNPC(tid); 354#endif 355 } | 154 // Get the size of an instruction. 155 instSize = sizeof(TheISA::MachInst); 156} 157 158template <class Impl> 159std::string 160DefaultFetch<Impl>::name() const 161{ --- 156 unchanged lines hidden (view full) --- 318 // Setup PC and nextPC with initial state. 319 for (int tid = 0; tid < numThreads; tid++) { 320 PC[tid] = cpu->readPC(tid); 321 nextPC[tid] = cpu->readNextPC(tid); 322#if ISA_HAS_DELAY_SLOT 323 nextNPC[tid] = cpu->readNextNPC(tid); 324#endif 325 } |
326 327 // Size of cache block. 328 cacheBlkSize = icachePort->peerBlockSize(); 329 330 // Create mask to get rid of offset bits. 331 cacheBlkMask = (cacheBlkSize - 1); 332 333 for (int tid=0; tid < numThreads; tid++) { 334 335 fetchStatus[tid] = Running; 336 337 priorityList.push_back(tid); 338 339 memReq[tid] = NULL; 340 341 // Create space to store a cache line. 342 cacheData[tid] = new uint8_t[cacheBlkSize]; 343 cacheDataPC[tid] = 0; 344 cacheDataValid[tid] = false; 345 346 delaySlotInfo[tid].branchSeqNum = -1; 347 delaySlotInfo[tid].numInsts = 0; 348 delaySlotInfo[tid].targetAddr = 0; 349 delaySlotInfo[tid].targetReady = false; 350 351 stalls[tid].decode = false; 352 stalls[tid].rename = false; 353 stalls[tid].iew = false; 354 stalls[tid].commit = false; 355 } |
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356} 357 358template<class Impl> 359void 360DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 361{ 362 unsigned tid = pkt->req->getThreadNum(); 363 --- 1117 unchanged lines hidden --- | 356} 357 358template<class Impl> 359void 360DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 361{ 362 unsigned tid = pkt->req->getThreadNum(); 363 --- 1117 unchanged lines hidden --- |