fetch_impl.hh (3594:e401993e0cbb) fetch_impl.hh (3633:524f2aadbc89)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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57 panic("DefaultFetch doesn't expect recvAtomic callback!");
58 return curTick;
59}
60
61template<class Impl>
62void
63DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
64{
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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57 panic("DefaultFetch doesn't expect recvAtomic callback!");
58 return curTick;
59}
60
61template<class Impl>
62void
63DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
64{
65 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
66 "functional call.");
65 warn("Default fetch doesn't update it's state from a functional call.");
67}
68
69template<class Impl>
70void
71DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
72{
73 if (status == RangeChange)
74 return;
75
76 panic("DefaultFetch doesn't expect recvStatusChange callback!");
77}
78
79template<class Impl>
80bool
81DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
82{
66}
67
68template<class Impl>
69void
70DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
71{
72 if (status == RangeChange)
73 return;
74
75 panic("DefaultFetch doesn't expect recvStatusChange callback!");
76}
77
78template<class Impl>
79bool
80DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
81{
83 DPRINTF(Fetch, "Received timing\n");
84 if (pkt->isResponse()) {
85 fetch->processCacheCompletion(pkt);
86 }
87 //else Snooped a coherence request, just return
88 return true;
89}
90
91template<class Impl>

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556
557template <class Impl>
558bool
559DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
560{
561 Fault fault = NoFault;
562
563 //AlphaDep
82 if (pkt->isResponse()) {
83 fetch->processCacheCompletion(pkt);
84 }
85 //else Snooped a coherence request, just return
86 return true;
87}
88
89template<class Impl>

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554
555template <class Impl>
556bool
557DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
558{
559 Fault fault = NoFault;
560
561 //AlphaDep
564 if (cacheBlocked || isSwitchedOut() ||
565 (interruptPending && (fetch_PC & 0x3))) {
562 if (cacheBlocked) {
563 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
564 tid);
565 return false;
566 } else if (isSwitchedOut()) {
567 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
568 tid);
569 return false;
570 } else if (interruptPending && !(fetch_PC & 0x3)) {
566 // Hold off fetch from getting new instructions when:
567 // Cache is blocked, or
568 // while an interrupt is pending and we're not in PAL mode, or
569 // fetch is switched out.
571 // Hold off fetch from getting new instructions when:
572 // Cache is blocked, or
573 // while an interrupt is pending and we're not in PAL mode, or
574 // fetch is switched out.
575 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
576 tid);
570 return false;
571 }
572
573 // Align the fetch PC so it's at the start of a cache block.
577 return false;
578 }
579
580 // Align the fetch PC so it's at the start of a cache block.
574 fetch_PC = icacheBlockAlignPC(fetch_PC);
581 Addr block_PC = icacheBlockAlignPC(fetch_PC);
575
576 // If we've already got the block, no need to try to fetch it again.
582
583 // If we've already got the block, no need to try to fetch it again.
577 if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
584 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
578 return true;
579 }
580
581 // Setup the memReq to do a read of the first instruction's address.
582 // Set the appropriate read size and flags as well.
583 // Build request here.
585 return true;
586 }
587
588 // Setup the memReq to do a read of the first instruction's address.
589 // Set the appropriate read size and flags as well.
590 // Build request here.
584 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0,
591 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
585 fetch_PC, cpu->readCpuId(), tid);
586
587 memReq[tid] = mem_req;
588
589 // Translate the instruction request.
590 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
591
592 // In the case of faults, the fetch stage may need to stall and wait

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606 }
607#endif
608
609 // Build packet here.
610 PacketPtr data_pkt = new Packet(mem_req,
611 Packet::ReadReq, Packet::Broadcast);
612 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
613
592 fetch_PC, cpu->readCpuId(), tid);
593
594 memReq[tid] = mem_req;
595
596 // Translate the instruction request.
597 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
598
599 // In the case of faults, the fetch stage may need to stall and wait

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613 }
614#endif
615
616 // Build packet here.
617 PacketPtr data_pkt = new Packet(mem_req,
618 Packet::ReadReq, Packet::Broadcast);
619 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
620
614 cacheDataPC[tid] = fetch_PC;
621 cacheDataPC[tid] = block_PC;
615 cacheDataValid[tid] = false;
616
617 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
618
619 fetchedCacheLines++;
620
621 // Now do the timing access to see whether or not the instruction
622 // exists within the cache.

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1047 } else {
1048 ++fetchMiscStallCycles;
1049 }
1050 return;
1051 }
1052 } else {
1053 if (fetchStatus[tid] == Idle) {
1054 ++fetchIdleCycles;
622 cacheDataValid[tid] = false;
623
624 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
625
626 fetchedCacheLines++;
627
628 // Now do the timing access to see whether or not the instruction
629 // exists within the cache.

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1054 } else {
1055 ++fetchMiscStallCycles;
1056 }
1057 return;
1058 }
1059 } else {
1060 if (fetchStatus[tid] == Idle) {
1061 ++fetchIdleCycles;
1062 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1055 } else if (fetchStatus[tid] == Blocked) {
1056 ++fetchBlockedCycles;
1063 } else if (fetchStatus[tid] == Blocked) {
1064 ++fetchBlockedCycles;
1065 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1057 } else if (fetchStatus[tid] == Squashing) {
1058 ++fetchSquashCycles;
1066 } else if (fetchStatus[tid] == Squashing) {
1067 ++fetchSquashCycles;
1068 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1059 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1060 ++icacheStallCycles;
1069 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1070 ++icacheStallCycles;
1071 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1061 }
1062
1063 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1064 // fetch should do nothing.
1065 return;
1066 }
1067
1068 ++fetchCycles;

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1155
1156 // Increment stat of fetched instructions.
1157 ++fetchedInsts;
1158
1159 // Move to the next instruction, unless we have a branch.
1160 fetch_PC = next_PC;
1161
1162 if (instruction->isQuiesce()) {
1072 }
1073
1074 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1075 // fetch should do nothing.
1076 return;
1077 }
1078
1079 ++fetchCycles;

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1166
1167 // Increment stat of fetched instructions.
1168 ++fetchedInsts;
1169
1170 // Move to the next instruction, unless we have a branch.
1171 fetch_PC = next_PC;
1172
1173 if (instruction->isQuiesce()) {
1163 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1164 curTick);
1174// warn("%lli: Quiesce instruction encountered, halting fetch!",
1175// curTick);
1165 fetchStatus[tid] = QuiescePending;
1166 ++numInst;
1167 status_change = true;
1168 break;
1169 }
1170
1171 offset += instSize;
1172

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1270
1271 toDecode->insts[numInst] = instruction;
1272 toDecode->size++;
1273
1274 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1275
1276 fetchStatus[tid] = TrapPending;
1277 status_change = true;
1176 fetchStatus[tid] = QuiescePending;
1177 ++numInst;
1178 status_change = true;
1179 break;
1180 }
1181
1182 offset += instSize;
1183

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1281
1282 toDecode->insts[numInst] = instruction;
1283 toDecode->size++;
1284
1285 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1286
1287 fetchStatus[tid] = TrapPending;
1288 status_change = true;
1278#else // !FULL_SYSTEM
1279 fetchStatus[tid] = TrapPending;
1280 status_change = true;
1281
1289
1290// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1291#else // !FULL_SYSTEM
1292 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1282#endif // FULL_SYSTEM
1293#endif // FULL_SYSTEM
1283 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1284 tid, fault->name(), PC[tid]);
1285 }
1286}
1287
1288template<class Impl>
1289void
1290DefaultFetch<Impl>::recvRetry()
1291{
1292 if (retryPkt != NULL) {

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1295}
1296
1297template<class Impl>
1298void
1299DefaultFetch<Impl>::recvRetry()
1300{
1301 if (retryPkt != NULL) {

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