fetch_impl.hh (3473:852a0bb230da) | fetch_impl.hh (3484:9b7ac1654430) |
---|---|
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 49 unchanged lines hidden (view full) --- 58 panic("DefaultFetch doesn't expect recvAtomic callback!"); 59 return curTick; 60} 61 62template<class Impl> 63void 64DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 65{ | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 49 unchanged lines hidden (view full) --- 58 panic("DefaultFetch doesn't expect recvAtomic callback!"); 59 return curTick; 60} 61 62template<class Impl> 63void 64DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 65{ |
66 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 67 "functional call."); | 66 warn("Default fetch doesn't update it's state from a functional call."); |
68} 69 70template<class Impl> 71void 72DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 73{ 74 if (status == RangeChange) 75 return; 76 77 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 78} 79 80template<class Impl> 81bool 82DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 83{ | 67} 68 69template<class Impl> 70void 71DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 72{ 73 if (status == RangeChange) 74 return; 75 76 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 77} 78 79template<class Impl> 80bool 81DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 82{ |
84 DPRINTF(Fetch, "Received timing\n"); | |
85 if (pkt->isResponse()) { 86 fetch->processCacheCompletion(pkt); 87 } 88 //else Snooped a coherence request, just return 89 return true; 90} 91 92template<class Impl> 93void 94DefaultFetch<Impl>::IcachePort::recvRetry() 95{ 96 fetch->recvRetry(); 97} 98 99template<class Impl> 100DefaultFetch<Impl>::DefaultFetch(Params *params) | 83 if (pkt->isResponse()) { 84 fetch->processCacheCompletion(pkt); 85 } 86 //else Snooped a coherence request, just return 87 return true; 88} 89 90template<class Impl> 91void 92DefaultFetch<Impl>::IcachePort::recvRetry() 93{ 94 fetch->recvRetry(); 95} 96 97template<class Impl> 98DefaultFetch<Impl>::DefaultFetch(Params *params) |
101 : mem(params->mem), 102 branchPred(params), | 99 : branchPred(params), |
103 decodeToFetchDelay(params->decodeToFetchDelay), 104 renameToFetchDelay(params->renameToFetchDelay), 105 iewToFetchDelay(params->iewToFetchDelay), 106 commitToFetchDelay(params->commitToFetchDelay), 107 fetchWidth(params->fetchWidth), 108 cacheBlocked(false), 109 retryPkt(NULL), 110 retryTid(-1), --- 1004 unchanged lines hidden (view full) --- 1115 1116 // Make sure this is a valid index. 1117 assert(offset <= cacheBlkSize - instSize); 1118 1119 // Get the instruction from the array of the cache line. 1120 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1121 (&cacheData[tid][offset])); 1122 | 100 decodeToFetchDelay(params->decodeToFetchDelay), 101 renameToFetchDelay(params->renameToFetchDelay), 102 iewToFetchDelay(params->iewToFetchDelay), 103 commitToFetchDelay(params->commitToFetchDelay), 104 fetchWidth(params->fetchWidth), 105 cacheBlocked(false), 106 retryPkt(NULL), 107 retryTid(-1), --- 1004 unchanged lines hidden (view full) --- 1112 1113 // Make sure this is a valid index. 1114 assert(offset <= cacheBlkSize - instSize); 1115 1116 // Get the instruction from the array of the cache line. 1117 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1118 (&cacheData[tid][offset])); 1119 |
1123 ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid)); | 1120#if THE_ISA == ALPHA_ISA 1121 ext_inst = TheISA::makeExtMI(inst, fetch_PC); 1122#elif THE_ISA == SPARC_ISA 1123 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); 1124#endif |
1124 1125 // Create a new DynInst from the instruction fetched. 1126 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, 1127 next_PC, 1128 inst_seq, cpu); 1129 instruction->setTid(tid); 1130 1131 instruction->setASID(tid); --- 26 unchanged lines hidden (view full) --- 1158 1159 // Increment stat of fetched instructions. 1160 ++fetchedInsts; 1161 1162 // Move to the next instruction, unless we have a branch. 1163 fetch_PC = next_PC; 1164 1165 if (instruction->isQuiesce()) { | 1125 1126 // Create a new DynInst from the instruction fetched. 1127 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, 1128 next_PC, 1129 inst_seq, cpu); 1130 instruction->setTid(tid); 1131 1132 instruction->setASID(tid); --- 26 unchanged lines hidden (view full) --- 1159 1160 // Increment stat of fetched instructions. 1161 ++fetchedInsts; 1162 1163 // Move to the next instruction, unless we have a branch. 1164 fetch_PC = next_PC; 1165 1166 if (instruction->isQuiesce()) { |
1166 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1167 curTick); | 1167// warn("%lli: Quiesce instruction encountered, halting fetch!", 1168// curTick); |
1168 fetchStatus[tid] = QuiescePending; 1169 ++numInst; 1170 status_change = true; 1171 break; 1172 } 1173 1174 offset += instSize; 1175 --- 97 unchanged lines hidden (view full) --- 1273 1274 toDecode->insts[numInst] = instruction; 1275 toDecode->size++; 1276 1277 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1278 1279 fetchStatus[tid] = TrapPending; 1280 status_change = true; | 1169 fetchStatus[tid] = QuiescePending; 1170 ++numInst; 1171 status_change = true; 1172 break; 1173 } 1174 1175 offset += instSize; 1176 --- 97 unchanged lines hidden (view full) --- 1274 1275 toDecode->insts[numInst] = instruction; 1276 toDecode->size++; 1277 1278 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1279 1280 fetchStatus[tid] = TrapPending; 1281 status_change = true; |
1281#else // !FULL_SYSTEM 1282 fetchStatus[tid] = TrapPending; 1283 status_change = true; | |
1284 | 1282 |
1283// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); 1284#else // !FULL_SYSTEM 1285 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]); |
|
1285#endif // FULL_SYSTEM | 1286#endif // FULL_SYSTEM |
1286 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", 1287 tid, fault->name(), PC[tid]); | |
1288 } 1289} 1290 1291template<class Impl> 1292void 1293DefaultFetch<Impl>::recvRetry() 1294{ 1295 if (retryPkt != NULL) { --- 162 unchanged lines hidden --- | 1287 } 1288} 1289 1290template<class Impl> 1291void 1292DefaultFetch<Impl>::recvRetry() 1293{ 1294 if (retryPkt != NULL) { --- 162 unchanged lines hidden --- |