fetch_impl.hh (3120:e49afeaf79e9) fetch_impl.hh (3125:febd811bccc6)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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437 delaySlotInfo[i].targetReady = false;
438#endif
439 fetchStatus[i] = Running;
440 }
441 numInst = 0;
442 wroteToTimeBuffer = false;
443 _status = Inactive;
444 switchedOut = false;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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437 delaySlotInfo[i].targetReady = false;
438#endif
439 fetchStatus[i] = Running;
440 }
441 numInst = 0;
442 wroteToTimeBuffer = false;
443 _status = Inactive;
444 switchedOut = false;
445 interruptPending = false;
445 branchPred.takeOverFrom();
446}
447
448template <class Impl>
449void
450DefaultFetch<Impl>::wakeFromQuiesce()
451{
452 DPRINTF(Fetch, "Waking up from quiesce\n");

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558
559#if FULL_SYSTEM
560 // Flag to say whether or not address is physical addr.
561 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
562#else
563 unsigned flags = 0;
564#endif // FULL_SYSTEM
565
446 branchPred.takeOverFrom();
447}
448
449template <class Impl>
450void
451DefaultFetch<Impl>::wakeFromQuiesce()
452{
453 DPRINTF(Fetch, "Waking up from quiesce\n");

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559
560#if FULL_SYSTEM
561 // Flag to say whether or not address is physical addr.
562 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
563#else
564 unsigned flags = 0;
565#endif // FULL_SYSTEM
566
566 if (cacheBlocked || (interruptPending && flags == 0)) {
567 if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
567 // Hold off fetch from getting new instructions when:
568 // Cache is blocked, or
569 // while an interrupt is pending and we're not in PAL mode, or
570 // fetch is switched out.
571 return false;
572 }
573
574 // Align the fetch PC so it's at the start of a cache block.

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1104
1105 // Make sure this is a valid index.
1106 assert(offset <= cacheBlkSize - instSize);
1107
1108 // Get the instruction from the array of the cache line.
1109 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1110 (&cacheData[tid][offset]));
1111
568 // Hold off fetch from getting new instructions when:
569 // Cache is blocked, or
570 // while an interrupt is pending and we're not in PAL mode, or
571 // fetch is switched out.
572 return false;
573 }
574
575 // Align the fetch PC so it's at the start of a cache block.

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1105
1106 // Make sure this is a valid index.
1107 assert(offset <= cacheBlkSize - instSize);
1108
1109 // Get the instruction from the array of the cache line.
1110 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1111 (&cacheData[tid][offset]));
1112
1112 ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid));
1113 ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1113
1114 // Create a new DynInst from the instruction fetched.
1115 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1116 next_PC,
1117 inst_seq, cpu);
1118 instruction->setTid(tid);
1119
1120 instruction->setASID(tid);

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1147
1148 // Increment stat of fetched instructions.
1149 ++fetchedInsts;
1150
1151 // Move to the next instruction, unless we have a branch.
1152 fetch_PC = next_PC;
1153
1154 if (instruction->isQuiesce()) {
1114
1115 // Create a new DynInst from the instruction fetched.
1116 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1117 next_PC,
1118 inst_seq, cpu);
1119 instruction->setTid(tid);
1120
1121 instruction->setASID(tid);

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1148
1149 // Increment stat of fetched instructions.
1150 ++fetchedInsts;
1151
1152 // Move to the next instruction, unless we have a branch.
1153 fetch_PC = next_PC;
1154
1155 if (instruction->isQuiesce()) {
1155 warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
1156 curTick);
1156// warn("%lli: Quiesce instruction encountered, halting fetch!",
1157// curTick);
1157 fetchStatus[tid] = QuiescePending;
1158 ++numInst;
1159 status_change = true;
1160 break;
1161 }
1162
1163 offset += instSize;
1164

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1263 toDecode->insts[numInst] = instruction;
1264 toDecode->size++;
1265
1266 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1267
1268 fetchStatus[tid] = TrapPending;
1269 status_change = true;
1270
1158 fetchStatus[tid] = QuiescePending;
1159 ++numInst;
1160 status_change = true;
1161 break;
1162 }
1163
1164 offset += instSize;
1165

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1264 toDecode->insts[numInst] = instruction;
1265 toDecode->size++;
1266
1267 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1268
1269 fetchStatus[tid] = TrapPending;
1270 status_change = true;
1271
1271 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1272// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1272#else // !FULL_SYSTEM
1273 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1274#endif // FULL_SYSTEM
1275 }
1276}
1277
1278template<class Impl>
1279void

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1274 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1275#endif // FULL_SYSTEM
1276 }
1277}
1278
1279template<class Impl>
1280void

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