fetch_impl.hh (2935:d1223a6c9156) fetch_impl.hh (2965:82703e01285a)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1203
1204 if (numInst > 0) {
1205 wroteToTimeBuffer = true;
1206 }
1207
1208 // Now that fetching is completed, update the PC to signify what the next
1209 // cycle will be.
1210 if (fault == NoFault) {
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1203
1204 if (numInst > 0) {
1205 wroteToTimeBuffer = true;
1206 }
1207
1208 // Now that fetching is completed, update the PC to signify what the next
1209 // cycle will be.
1210 if (fault == NoFault) {
1211 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1212
1213#if THE_ISA == ALPHA_ISA
1211#if THE_ISA == ALPHA_ISA
1212 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1214 PC[tid] = next_PC;
1215 nextPC[tid] = next_PC + instSize;
1216#else
1217 if (delaySlotInfo[tid].targetReady &&
1218 delaySlotInfo[tid].numInsts == 0) {
1219 // Set PC to target
1220 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1221 nextPC[tid] = next_PC + instSize; //next_NPC
1222 nextNPC[tid] = next_PC + (2 * instSize);
1223
1224 delaySlotInfo[tid].targetReady = false;
1225 } else {
1226 PC[tid] = next_PC;
1227 nextPC[tid] = next_NPC;
1228 nextNPC[tid] = next_NPC + instSize;
1229 }
1213 PC[tid] = next_PC;
1214 nextPC[tid] = next_PC + instSize;
1215#else
1216 if (delaySlotInfo[tid].targetReady &&
1217 delaySlotInfo[tid].numInsts == 0) {
1218 // Set PC to target
1219 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1220 nextPC[tid] = next_PC + instSize; //next_NPC
1221 nextNPC[tid] = next_PC + (2 * instSize);
1222
1223 delaySlotInfo[tid].targetReady = false;
1224 } else {
1225 PC[tid] = next_PC;
1226 nextPC[tid] = next_NPC;
1227 nextNPC[tid] = next_NPC + instSize;
1228 }
1229
1230 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1230#endif
1231 } else {
1232 // We shouldn't be in an icache miss and also have a fault (an ITB
1233 // miss)
1234 if (fetchStatus[tid] == IcacheWaitResponse) {
1235 panic("Fetch should have exited prior to this!");
1236 }
1237

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1265 toDecode->insts[numInst] = instruction;
1266 toDecode->size++;
1267
1268 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1269
1270 fetchStatus[tid] = TrapPending;
1271 status_change = true;
1272
1231#endif
1232 } else {
1233 // We shouldn't be in an icache miss and also have a fault (an ITB
1234 // miss)
1235 if (fetchStatus[tid] == IcacheWaitResponse) {
1236 panic("Fetch should have exited prior to this!");
1237 }
1238

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1266 toDecode->insts[numInst] = instruction;
1267 toDecode->size++;
1268
1269 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1270
1271 fetchStatus[tid] = TrapPending;
1272 status_change = true;
1273
1273 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1274 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1274#else // !FULL_SYSTEM
1275#else // !FULL_SYSTEM
1275 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1276 warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1276#endif // FULL_SYSTEM
1277 }
1278}
1279
1280template<class Impl>
1281void
1282DefaultFetch<Impl>::recvRetry()
1283{

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1278 }
1279}
1280
1281template<class Impl>
1282void
1283DefaultFetch<Impl>::recvRetry()
1284{

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