fetch_impl.hh (2906:3d65b80fdb11) fetch_impl.hh (2935:d1223a6c9156)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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160
161 memReq[tid] = NULL;
162
163 // Create space to store a cache line.
164 cacheData[tid] = new uint8_t[cacheBlkSize];
165 cacheDataPC[tid] = 0;
166 cacheDataValid[tid] = false;
167
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 151 unchanged lines hidden (view full) ---

160
161 memReq[tid] = NULL;
162
163 // Create space to store a cache line.
164 cacheData[tid] = new uint8_t[cacheBlkSize];
165 cacheDataPC[tid] = 0;
166 cacheDataValid[tid] = false;
167
168 stalls[tid].decode = 0;
169 stalls[tid].rename = 0;
170 stalls[tid].iew = 0;
171 stalls[tid].commit = 0;
168 delaySlotInfo[tid].branchSeqNum = -1;
169 delaySlotInfo[tid].numInsts = 0;
170 delaySlotInfo[tid].targetAddr = 0;
171 delaySlotInfo[tid].targetReady = false;
172
173 stalls[tid].decode = false;
174 stalls[tid].rename = false;
175 stalls[tid].iew = false;
176 stalls[tid].commit = false;
172 }
173
174 // Get the size of an instruction.
175 instSize = sizeof(MachInst);
176}
177
178template <class Impl>
179std::string

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283 icachePort = new IcachePort(this);
284
285#if USE_CHECKER
286 if (cpu->checker) {
287 cpu->checker->setIcachePort(icachePort);
288 }
289#endif
290
177 }
178
179 // Get the size of an instruction.
180 instSize = sizeof(MachInst);
181}
182
183template <class Impl>
184std::string

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288 icachePort = new IcachePort(this);
289
290#if USE_CHECKER
291 if (cpu->checker) {
292 cpu->checker->setIcachePort(icachePort);
293 }
294#endif
295
296 // Schedule fetch to get the correct PC from the CPU
297 // scheduleFetchStartupEvent(1);
298
291 // Fetch needs to start fetching instructions at the very beginning,
292 // so it must start up in active state.
293 switchToActive();
294}
295
296template<class Impl>
297void
298DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)

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421 stalls[i].decode = 0;
422 stalls[i].rename = 0;
423 stalls[i].iew = 0;
424 stalls[i].commit = 0;
425 PC[i] = cpu->readPC(i);
426 nextPC[i] = cpu->readNextPC(i);
427#if THE_ISA != ALPHA_ISA
428 nextNPC[i] = cpu->readNextNPC(i);
299 // Fetch needs to start fetching instructions at the very beginning,
300 // so it must start up in active state.
301 switchToActive();
302}
303
304template<class Impl>
305void
306DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)

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429 stalls[i].decode = 0;
430 stalls[i].rename = 0;
431 stalls[i].iew = 0;
432 stalls[i].commit = 0;
433 PC[i] = cpu->readPC(i);
434 nextPC[i] = cpu->readNextPC(i);
435#if THE_ISA != ALPHA_ISA
436 nextNPC[i] = cpu->readNextNPC(i);
437 delaySlotInfo[i].branchSeqNum = -1;
438 delaySlotInfo[i].numInsts = 0;
439 delaySlotInfo[i].targetAddr = 0;
440 delaySlotInfo[i].targetReady = false;
429#endif
430 fetchStatus[i] = Running;
431 }
432 numInst = 0;
433 wroteToTimeBuffer = false;
434 _status = Inactive;
435 switchedOut = false;
436 branchPred.takeOverFrom();

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469 cpu->deactivateStage(O3CPU::FetchIdx);
470
471 _status = Inactive;
472 }
473}
474
475template <class Impl>
476bool
441#endif
442 fetchStatus[i] = Running;
443 }
444 numInst = 0;
445 wroteToTimeBuffer = false;
446 _status = Inactive;
447 switchedOut = false;
448 branchPred.takeOverFrom();

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481 cpu->deactivateStage(O3CPU::FetchIdx);
482
483 _status = Inactive;
484 }
485}
486
487template <class Impl>
488bool
477DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
489DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
490 Addr &next_NPC)
478{
479 // Do branch prediction check here.
480 // A bit of a misnomer...next_PC is actually the current PC until
481 // this function updates it.
482 bool predict_taken;
483
484 if (!inst->isControl()) {
491{
492 // Do branch prediction check here.
493 // A bit of a misnomer...next_PC is actually the current PC until
494 // this function updates it.
495 bool predict_taken;
496
497 if (!inst->isControl()) {
498#if THE_ISA == ALPHA_ISA
485 next_PC = next_PC + instSize;
486 inst->setPredTarg(next_PC);
499 next_PC = next_PC + instSize;
500 inst->setPredTarg(next_PC);
501#else
502 Addr cur_PC = next_PC;
503 next_PC = cur_PC + instSize; //next_NPC;
504 next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
505 inst->setPredTarg(next_NPC);
506#endif
487 return false;
488 }
489
507 return false;
508 }
509
490 predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
510 int tid = inst->threadNumber;
511#if THE_ISA == ALPHA_ISA
512 predict_taken = branchPred.predict(inst, next_PC, tid);
513#else
514 Addr pred_PC = next_PC;
515 predict_taken = branchPred.predict(inst, pred_PC, tid);
491
516
517 if (predict_taken) {
518 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
519 } else {
520 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
521 }
522
523 if (predict_taken) {
524 next_PC = next_NPC;
525 next_NPC = pred_PC;
526
527 // Update delay slot info
528 ++delaySlotInfo[tid].numInsts;
529 delaySlotInfo[tid].targetAddr = pred_PC;
530 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
531 delaySlotInfo[tid].numInsts);
532 } else { // !predict_taken
533 if (inst->isCondDelaySlot()) {
534 next_PC = pred_PC;
535 // The delay slot is skipped here if there is on
536 // prediction
537 } else {
538 next_PC = next_NPC;
539 // No need to declare a delay slot here since
540 // there is no for the pred. target to jump
541 }
542
543 next_NPC = next_NPC + instSize;
544 }
545#endif
546
492 ++fetchedBranches;
493
494 if (predict_taken) {
495 ++predictedBranches;
496 }
497
498 return predict_taken;
499}

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601inline void
602DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
603{
604 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
605 tid, new_PC);
606
607 PC[tid] = new_PC;
608 nextPC[tid] = new_PC + instSize;
547 ++fetchedBranches;
548
549 if (predict_taken) {
550 ++predictedBranches;
551 }
552
553 return predict_taken;
554}

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656inline void
657DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
658{
659 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
660 tid, new_PC);
661
662 PC[tid] = new_PC;
663 nextPC[tid] = new_PC + instSize;
664 nextNPC[tid] = new_PC + (2 * instSize);
609
610 // Clear the icache miss if it's outstanding.
611 if (fetchStatus[tid] == IcacheWaitResponse) {
612 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
613 tid);
614 memReq[tid] = NULL;
615 }
616

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634DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
635 const InstSeqNum &seq_num,
636 unsigned tid)
637{
638 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
639
640 doSquash(new_PC, tid);
641
665
666 // Clear the icache miss if it's outstanding.
667 if (fetchStatus[tid] == IcacheWaitResponse) {
668 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
669 tid);
670 memReq[tid] = NULL;
671 }
672

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690DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
691 const InstSeqNum &seq_num,
692 unsigned tid)
693{
694 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
695
696 doSquash(new_PC, tid);
697
698#if THE_ISA != ALPHA_ISA
699 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
700 delaySlotInfo[tid].numInsts = 0;
701 delaySlotInfo[tid].targetAddr = 0;
702 delaySlotInfo[tid].targetReady = false;
703 }
704#endif
705
642 // Tell the CPU to remove any instructions that are in flight between
643 // fetch and decode.
644 cpu->removeInstsUntil(seq_num, tid);
645}
646
647template<class Impl>
648bool
649DefaultFetch<Impl>::checkStall(unsigned tid) const

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707 cpu->deactivateStage(O3CPU::FetchIdx);
708 }
709
710 return Inactive;
711}
712
713template <class Impl>
714void
706 // Tell the CPU to remove any instructions that are in flight between
707 // fetch and decode.
708 cpu->removeInstsUntil(seq_num, tid);
709}
710
711template<class Impl>
712bool
713DefaultFetch<Impl>::checkStall(unsigned tid) const

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771 cpu->deactivateStage(O3CPU::FetchIdx);
772 }
773
774 return Inactive;
775}
776
777template <class Impl>
778void
715DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
779DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
780 bool squash_delay_slot, unsigned tid)
716{
717 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
718
719 doSquash(new_PC, tid);
720
781{
782 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
783
784 doSquash(new_PC, tid);
785
786#if THE_ISA == ALPHA_ISA
721 // Tell the CPU to remove any instructions that are not in the ROB.
787 // Tell the CPU to remove any instructions that are not in the ROB.
722 cpu->removeInstsNotInROB(tid);
788 cpu->removeInstsNotInROB(tid, true, 0);
789#else
790 if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
791 delaySlotInfo[tid].numInsts = 0;
792 delaySlotInfo[tid].targetAddr = 0;
793 delaySlotInfo[tid].targetReady = false;
794 }
795
796 // Tell the CPU to remove any instructions that are not in the ROB.
797 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
798#endif
723}
724
725template <class Impl>
726void
727DefaultFetch<Impl>::tick()
728{
729 list<unsigned>::iterator threads = (*activeThreads).begin();
730 bool status_change = false;

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823 }
824
825 // Check squash signals from commit.
826 if (fromCommit->commitInfo[tid].squash) {
827
828 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
829 "from commit.\n",tid);
830
799}
800
801template <class Impl>
802void
803DefaultFetch<Impl>::tick()
804{
805 list<unsigned>::iterator threads = (*activeThreads).begin();
806 bool status_change = false;

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899 }
900
901 // Check squash signals from commit.
902 if (fromCommit->commitInfo[tid].squash) {
903
904 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
905 "from commit.\n",tid);
906
907#if THE_ISA == ALPHA_ISA
908 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
909#else
910 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
911#endif
831 // In any case, squash.
912 // In any case, squash.
832 squash(fromCommit->commitInfo[tid].nextPC,tid);
913 squash(fromCommit->commitInfo[tid].nextPC,
914 doneSeqNum,
915 fromCommit->commitInfo[tid].squashDelaySlot,
916 tid);
833
834 // Also check if there's a mispredict that happened.
835 if (fromCommit->commitInfo[tid].branchMispredict) {
836 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
837 fromCommit->commitInfo[tid].nextPC,
838 fromCommit->commitInfo[tid].branchTaken,
839 tid);
840 } else {

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871 fromDecode->decodeInfo[tid].branchTaken,
872 tid);
873 } else {
874 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
875 tid);
876 }
877
878 if (fetchStatus[tid] != Squashing) {
917
918 // Also check if there's a mispredict that happened.
919 if (fromCommit->commitInfo[tid].branchMispredict) {
920 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
921 fromCommit->commitInfo[tid].nextPC,
922 fromCommit->commitInfo[tid].branchTaken,
923 tid);
924 } else {

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955 fromDecode->decodeInfo[tid].branchTaken,
956 tid);
957 } else {
958 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
959 tid);
960 }
961
962 if (fetchStatus[tid] != Squashing) {
963
964#if THE_ISA == ALPHA_ISA
965 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
966#else
967 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
968#endif
879 // Squash unless we're already squashing
880 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
969 // Squash unless we're already squashing
970 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
881 fromDecode->decodeInfo[tid].doneSeqNum,
971 doneSeqNum,
882 tid);
883
884 return true;
885 }
886 }
887
888 if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
889 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);

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979 // If we had a stall due to an icache miss, then return.
980 if (fetchStatus[tid] == IcacheWaitResponse) {
981 ++icacheStallCycles;
982 status_change = true;
983 return;
984 }
985
986 Addr next_PC = fetch_PC;
972 tid);
973
974 return true;
975 }
976 }
977
978 if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
979 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);

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1069 // If we had a stall due to an icache miss, then return.
1070 if (fetchStatus[tid] == IcacheWaitResponse) {
1071 ++icacheStallCycles;
1072 status_change = true;
1073 return;
1074 }
1075
1076 Addr next_PC = fetch_PC;
1077 Addr next_NPC = next_PC + instSize;
987 InstSeqNum inst_seq;
988 MachInst inst;
989 ExtMachInst ext_inst;
990 // @todo: Fix this hack.
991 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
992
993 if (fault == NoFault) {
994 // If the read of the first instruction was successful, then grab the
995 // instructions from the rest of the cache line and put them into the
996 // queue heading to decode.
997
998 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
999 "decode.\n",tid);
1000
1001 // Need to keep track of whether or not a predicted branch
1002 // ended this fetch block.
1003 bool predicted_branch = false;
1004
1078 InstSeqNum inst_seq;
1079 MachInst inst;
1080 ExtMachInst ext_inst;
1081 // @todo: Fix this hack.
1082 unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1083
1084 if (fault == NoFault) {
1085 // If the read of the first instruction was successful, then grab the
1086 // instructions from the rest of the cache line and put them into the
1087 // queue heading to decode.
1088
1089 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1090 "decode.\n",tid);
1091
1092 // Need to keep track of whether or not a predicted branch
1093 // ended this fetch block.
1094 bool predicted_branch = false;
1095
1096 // Need to keep track of whether or not a delay slot
1097 // instruction has been fetched
1098
1005 for (;
1006 offset < cacheBlkSize &&
1007 numInst < fetchWidth &&
1099 for (;
1100 offset < cacheBlkSize &&
1101 numInst < fetchWidth &&
1008 !predicted_branch;
1102 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1009 ++numInst) {
1010
1011 // Get a sequence number.
1012 inst_seq = cpu->getAndIncrementInstSeq();
1013
1014 // Make sure this is a valid index.
1015 assert(offset <= cacheBlkSize - instSize);
1016

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1037 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1038 tid, instruction->staticInst->disassemble(fetch_PC));
1039
1040 instruction->traceData =
1041 Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
1042 instruction->staticInst,
1043 instruction->readPC(),tid);
1044
1103 ++numInst) {
1104
1105 // Get a sequence number.
1106 inst_seq = cpu->getAndIncrementInstSeq();
1107
1108 // Make sure this is a valid index.
1109 assert(offset <= cacheBlkSize - instSize);
1110

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1131 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1132 tid, instruction->staticInst->disassemble(fetch_PC));
1133
1134 instruction->traceData =
1135 Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
1136 instruction->staticInst,
1137 instruction->readPC(),tid);
1138
1045 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
1139 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1140 next_NPC);
1046
1047 // Add instruction to the CPU's list of instructions.
1048 instruction->setInstListIt(cpu->addInst(instruction));
1049
1050 // Write the instruction to the first slot in the queue
1051 // that heads to decode.
1052 toDecode->insts[numInst] = instruction;
1053

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1063 warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
1064 curTick);
1065 fetchStatus[tid] = QuiescePending;
1066 ++numInst;
1067 status_change = true;
1068 break;
1069 }
1070
1141
1142 // Add instruction to the CPU's list of instructions.
1143 instruction->setInstListIt(cpu->addInst(instruction));
1144
1145 // Write the instruction to the first slot in the queue
1146 // that heads to decode.
1147 toDecode->insts[numInst] = instruction;
1148

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1158 warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
1159 curTick);
1160 fetchStatus[tid] = QuiescePending;
1161 ++numInst;
1162 status_change = true;
1163 break;
1164 }
1165
1071 offset+= instSize;
1166 offset += instSize;
1167
1168#if THE_ISA != ALPHA_ISA
1169 if (predicted_branch) {
1170 delaySlotInfo[tid].branchSeqNum = inst_seq;
1171
1172 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1173 tid, inst_seq);
1174 continue;
1175 } else if (delaySlotInfo[tid].numInsts > 0) {
1176 --delaySlotInfo[tid].numInsts;
1177
1178 // It's OK to set PC to target of branch
1179 if (delaySlotInfo[tid].numInsts == 0) {
1180 delaySlotInfo[tid].targetReady = true;
1181
1182 // Break the looping condition
1183 predicted_branch = true;
1184 }
1185
1186 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1187 " process.\n", tid, delaySlotInfo[tid].numInsts);
1188 }
1189#endif
1072 }
1190 }
1191
1192 if (offset >= cacheBlkSize) {
1193 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1194 "block.\n", tid);
1195 } else if (numInst >= fetchWidth) {
1196 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1197 "for this cycle.\n", tid);
1198 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1199 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1200 "instruction encountered.\n", tid);
1201 }
1073 }
1074
1075 if (numInst > 0) {
1076 wroteToTimeBuffer = true;
1077 }
1078
1079 // Now that fetching is completed, update the PC to signify what the next
1080 // cycle will be.
1081 if (fault == NoFault) {
1082 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1083
1084#if THE_ISA == ALPHA_ISA
1085 PC[tid] = next_PC;
1086 nextPC[tid] = next_PC + instSize;
1087#else
1202 }
1203
1204 if (numInst > 0) {
1205 wroteToTimeBuffer = true;
1206 }
1207
1208 // Now that fetching is completed, update the PC to signify what the next
1209 // cycle will be.
1210 if (fault == NoFault) {
1211 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1212
1213#if THE_ISA == ALPHA_ISA
1214 PC[tid] = next_PC;
1215 nextPC[tid] = next_PC + instSize;
1216#else
1088 PC[tid] = next_PC;
1089 nextPC[tid] = next_PC + instSize;
1090 nextPC[tid] = next_PC + instSize;
1217 if (delaySlotInfo[tid].targetReady &&
1218 delaySlotInfo[tid].numInsts == 0) {
1219 // Set PC to target
1220 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1221 nextPC[tid] = next_PC + instSize; //next_NPC
1222 nextNPC[tid] = next_PC + (2 * instSize);
1091
1223
1092 thread->setNextPC(thread->readNextNPC());
1093 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
1224 delaySlotInfo[tid].targetReady = false;
1225 } else {
1226 PC[tid] = next_PC;
1227 nextPC[tid] = next_NPC;
1228 nextNPC[tid] = next_NPC + instSize;
1229 }
1094#endif
1095 } else {
1096 // We shouldn't be in an icache miss and also have a fault (an ITB
1097 // miss)
1098 if (fetchStatus[tid] == IcacheWaitResponse) {
1099 panic("Fetch should have exited prior to this!");
1100 }
1101

--- 209 unchanged lines hidden --- 		1230#endif
1231 } else {
1232 // We shouldn't be in an icache miss and also have a fault (an ITB
1233 // miss)
1234 if (fetchStatus[tid] == IcacheWaitResponse) {
1235 panic("Fetch should have exited prior to this!");
1236 }
1237

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