fetch_impl.hh (2893:58c423134221) fetch_impl.hh (2894:a83675362809)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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352 pkt->req != memReq[tid] ||
353 isSwitchedOut()) {
354 ++fetchIcacheSquashes;
355 delete pkt->req;
356 delete pkt;
357 return;
358 }
359
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 343 unchanged lines hidden (view full) ---

352 pkt->req != memReq[tid] ||
353 isSwitchedOut()) {
354 ++fetchIcacheSquashes;
355 delete pkt->req;
356 delete pkt;
357 return;
358 }
359
360 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
361
360 if (!drainPending) {
361 // Wake up the CPU (if it went to sleep and was waiting on
362 // this completion event).
363 cpu->wakeCPU();
364
365 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
366 tid);
367

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512 // while an interrupt is pending and we're not in PAL mode, or
513 // fetch is switched out.
514 return false;
515 }
516
517 // Align the fetch PC so it's at the start of a cache block.
518 fetch_PC = icacheBlockAlignPC(fetch_PC);
519
362 if (!drainPending) {
363 // Wake up the CPU (if it went to sleep and was waiting on
364 // this completion event).
365 cpu->wakeCPU();
366
367 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
368 tid);
369

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514 // while an interrupt is pending and we're not in PAL mode, or
515 // fetch is switched out.
516 return false;
517 }
518
519 // Align the fetch PC so it's at the start of a cache block.
520 fetch_PC = icacheBlockAlignPC(fetch_PC);
521
520 // If we've already got the block, no need to try to fetch it again.
521 if (fetch_PC == cacheDataPC[tid]) {
522 return true;
523 }
524
525 // Setup the memReq to do a read of the first instruction's address.
526 // Set the appropriate read size and flags as well.
527 // Build request here.
528 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
529 fetch_PC, cpu->readCpuId(), tid);
530
531 memReq[tid] = mem_req;
532

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548 ret_fault = TheISA::genMachineCheckFault();
549 return false;
550 }
551#endif
552
553 // Build packet here.
554 PacketPtr data_pkt = new Packet(mem_req,
555 Packet::ReadReq, Packet::Broadcast);
522 // Setup the memReq to do a read of the first instruction's address.
523 // Set the appropriate read size and flags as well.
524 // Build request here.
525 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
526 fetch_PC, cpu->readCpuId(), tid);
527
528 memReq[tid] = mem_req;
529

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545 ret_fault = TheISA::genMachineCheckFault();
546 return false;
547 }
548#endif
549
550 // Build packet here.
551 PacketPtr data_pkt = new Packet(mem_req,
552 Packet::ReadReq, Packet::Broadcast);
556 data_pkt->dataStatic(cacheData[tid]);
553 data_pkt->dataDynamic(new uint8_t[cacheBlkSize]);
557
554
558 cacheDataPC[tid] = fetch_PC;
559
560 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
561
562 fetchedCacheLines++;
563
564 // Now do the timing access to see whether or not the instruction
565 // exists within the cache.
566 if (!icachePort->sendTiming(data_pkt)) {
567 assert(retryPkt == NULL);

--- 737 unchanged lines hidden --- 		555 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
556
557 fetchedCacheLines++;
558
559 // Now do the timing access to see whether or not the instruction
560 // exists within the cache.
561 if (!icachePort->sendTiming(data_pkt)) {
562 assert(retryPkt == NULL);

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