fetch_impl.hh (2733:e0eac8fc5774) | fetch_impl.hh (2756:7bf0d6481df9) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 12 unchanged lines hidden (view full) --- 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 12 unchanged lines hidden (view full) --- 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim |
29 * Korey Sewell |
|
29 */ 30 | 30 */ 31 |
31#include "config/use_checker.hh" 32 | |
33#include "arch/isa_traits.hh" 34#include "arch/utility.hh" 35#include "cpu/checker/cpu.hh" 36#include "cpu/exetrace.hh" 37#include "cpu/o3/fetch.hh" 38#include "mem/packet.hh" 39#include "mem/request.hh" 40#include "sim/byteswap.hh" --- 224 unchanged lines hidden (view full) --- 265 .flags(Stats::total); 266 fetchRate = fetchedInsts / cpu->numCycles; 267 268 branchPred.regStats(); 269} 270 271template<class Impl> 272void | 32#include "arch/isa_traits.hh" 33#include "arch/utility.hh" 34#include "cpu/checker/cpu.hh" 35#include "cpu/exetrace.hh" 36#include "cpu/o3/fetch.hh" 37#include "mem/packet.hh" 38#include "mem/request.hh" 39#include "sim/byteswap.hh" --- 224 unchanged lines hidden (view full) --- 264 .flags(Stats::total); 265 fetchRate = fetchedInsts / cpu->numCycles; 266 267 branchPred.regStats(); 268} 269 270template<class Impl> 271void |
273DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr) | 272DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr) |
274{ 275 DPRINTF(Fetch, "Setting the CPU pointer.\n"); 276 cpu = cpu_ptr; 277 278 // Name is finally available, so create the port. 279 icachePort = new IcachePort(this); 280 281 Port *mem_dport = mem->getPort(""); 282 icachePort->setPeer(mem_dport); 283 mem_dport->setPeer(icachePort); 284 | 273{ 274 DPRINTF(Fetch, "Setting the CPU pointer.\n"); 275 cpu = cpu_ptr; 276 277 // Name is finally available, so create the port. 278 icachePort = new IcachePort(this); 279 280 Port *mem_dport = mem->getPort(""); 281 icachePort->setPeer(mem_dport); 282 mem_dport->setPeer(icachePort); 283 |
285#if USE_CHECKER | |
286 if (cpu->checker) { 287 cpu->checker->setIcachePort(icachePort); 288 } | 284 if (cpu->checker) { 285 cpu->checker->setIcachePort(icachePort); 286 } |
289#endif | |
290 291 // Fetch needs to start fetching instructions at the very beginning, 292 // so it must start up in active state. 293 switchToActive(); 294} 295 296template<class Impl> 297void --- 31 unchanged lines hidden (view full) --- 329template<class Impl> 330void 331DefaultFetch<Impl>::initStage() 332{ 333 // Setup PC and nextPC with initial state. 334 for (int tid = 0; tid < numThreads; tid++) { 335 PC[tid] = cpu->readPC(tid); 336 nextPC[tid] = cpu->readNextPC(tid); | 287 288 // Fetch needs to start fetching instructions at the very beginning, 289 // so it must start up in active state. 290 switchToActive(); 291} 292 293template<class Impl> 294void --- 31 unchanged lines hidden (view full) --- 326template<class Impl> 327void 328DefaultFetch<Impl>::initStage() 329{ 330 // Setup PC and nextPC with initial state. 331 for (int tid = 0; tid < numThreads; tid++) { 332 PC[tid] = cpu->readPC(tid); 333 nextPC[tid] = cpu->readNextPC(tid); |
334#if THE_ISA != ALPHA_ISA 335 nextNPC[tid] = cpu->readNextNPC(tid); 336#endif |
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337 } 338} 339 340template<class Impl> 341void 342DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 343{ 344 unsigned tid = pkt->req->getThreadNum(); --- 58 unchanged lines hidden (view full) --- 403 // Reset all state 404 for (int i = 0; i < Impl::MaxThreads; ++i) { 405 stalls[i].decode = 0; 406 stalls[i].rename = 0; 407 stalls[i].iew = 0; 408 stalls[i].commit = 0; 409 PC[i] = cpu->readPC(i); 410 nextPC[i] = cpu->readNextPC(i); | 337 } 338} 339 340template<class Impl> 341void 342DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 343{ 344 unsigned tid = pkt->req->getThreadNum(); --- 58 unchanged lines hidden (view full) --- 403 // Reset all state 404 for (int i = 0; i < Impl::MaxThreads; ++i) { 405 stalls[i].decode = 0; 406 stalls[i].rename = 0; 407 stalls[i].iew = 0; 408 stalls[i].commit = 0; 409 PC[i] = cpu->readPC(i); 410 nextPC[i] = cpu->readNextPC(i); |
411#if THE_ISA != ALPHA_ISA 412 nextNPC[i] = cpu->readNextNPC(i); 413#endif |
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411 fetchStatus[i] = Running; 412 } 413 numInst = 0; 414 wroteToTimeBuffer = false; 415 _status = Inactive; 416 switchedOut = false; 417 branchPred.takeOverFrom(); 418} --- 10 unchanged lines hidden (view full) --- 429 430template <class Impl> 431inline void 432DefaultFetch<Impl>::switchToActive() 433{ 434 if (_status == Inactive) { 435 DPRINTF(Activity, "Activating stage.\n"); 436 | 414 fetchStatus[i] = Running; 415 } 416 numInst = 0; 417 wroteToTimeBuffer = false; 418 _status = Inactive; 419 switchedOut = false; 420 branchPred.takeOverFrom(); 421} --- 10 unchanged lines hidden (view full) --- 432 433template <class Impl> 434inline void 435DefaultFetch<Impl>::switchToActive() 436{ 437 if (_status == Inactive) { 438 DPRINTF(Activity, "Activating stage.\n"); 439 |
437 cpu->activateStage(O3CPU::FetchIdx); | 440 cpu->activateStage(FullCPU::FetchIdx); |
438 439 _status = Active; 440 } 441} 442 443template <class Impl> 444inline void 445DefaultFetch<Impl>::switchToInactive() 446{ 447 if (_status == Active) { 448 DPRINTF(Activity, "Deactivating stage.\n"); 449 | 441 442 _status = Active; 443 } 444} 445 446template <class Impl> 447inline void 448DefaultFetch<Impl>::switchToInactive() 449{ 450 if (_status == Active) { 451 DPRINTF(Activity, "Deactivating stage.\n"); 452 |
450 cpu->deactivateStage(O3CPU::FetchIdx); | 453 cpu->deactivateStage(FullCPU::FetchIdx); |
451 452 _status = Inactive; 453 } 454} 455 456template <class Impl> 457bool 458DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC) --- 202 unchanged lines hidden (view full) --- 661 if (_status == Inactive) { 662 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 663 664 if (fetchStatus[tid] == IcacheAccessComplete) { 665 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 666 "completion\n",tid); 667 } 668 | 454 455 _status = Inactive; 456 } 457} 458 459template <class Impl> 460bool 461DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC) --- 202 unchanged lines hidden (view full) --- 664 if (_status == Inactive) { 665 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 666 667 if (fetchStatus[tid] == IcacheAccessComplete) { 668 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 669 "completion\n",tid); 670 } 671 |
669 cpu->activateStage(O3CPU::FetchIdx); | 672 cpu->activateStage(FullCPU::FetchIdx); |
670 } 671 672 return Active; 673 } 674 } 675 676 // Stage is switching from active to inactive, notify CPU of it. 677 if (_status == Active) { 678 DPRINTF(Activity, "Deactivating stage.\n"); 679 | 673 } 674 675 return Active; 676 } 677 } 678 679 // Stage is switching from active to inactive, notify CPU of it. 680 if (_status == Active) { 681 DPRINTF(Activity, "Deactivating stage.\n"); 682 |
680 cpu->deactivateStage(O3CPU::FetchIdx); | 683 cpu->deactivateStage(FullCPU::FetchIdx); |
681 } 682 683 return Inactive; 684} 685 686template <class Impl> 687void 688DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid) --- 334 unchanged lines hidden (view full) --- 1023 1024 // Increment stat of fetched instructions. 1025 ++fetchedInsts; 1026 1027 // Move to the next instruction, unless we have a branch. 1028 fetch_PC = next_PC; 1029 1030 if (instruction->isQuiesce()) { | 684 } 685 686 return Inactive; 687} 688 689template <class Impl> 690void 691DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid) --- 334 unchanged lines hidden (view full) --- 1026 1027 // Increment stat of fetched instructions. 1028 ++fetchedInsts; 1029 1030 // Move to the next instruction, unless we have a branch. 1031 fetch_PC = next_PC; 1032 1033 if (instruction->isQuiesce()) { |
1031 warn("%lli: Quiesce instruction encountered, halting fetch!", | 1034 warn("cycle %lli: Quiesce instruction encountered, halting fetch!", |
1032 curTick); 1033 fetchStatus[tid] = QuiescePending; 1034 ++numInst; 1035 status_change = true; 1036 break; 1037 } 1038 1039 offset+= instSize; --- 4 unchanged lines hidden (view full) --- 1044 wroteToTimeBuffer = true; 1045 } 1046 1047 // Now that fetching is completed, update the PC to signify what the next 1048 // cycle will be. 1049 if (fault == NoFault) { 1050 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC); 1051 | 1035 curTick); 1036 fetchStatus[tid] = QuiescePending; 1037 ++numInst; 1038 status_change = true; 1039 break; 1040 } 1041 1042 offset+= instSize; --- 4 unchanged lines hidden (view full) --- 1047 wroteToTimeBuffer = true; 1048 } 1049 1050 // Now that fetching is completed, update the PC to signify what the next 1051 // cycle will be. 1052 if (fault == NoFault) { 1053 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC); 1054 |
1055#if THE_ISA == ALPHA_ISA |
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1052 PC[tid] = next_PC; 1053 nextPC[tid] = next_PC + instSize; | 1056 PC[tid] = next_PC; 1057 nextPC[tid] = next_PC + instSize; |
1058#else 1059 PC[tid] = next_PC; 1060 nextPC[tid] = next_PC + instSize; 1061 nextPC[tid] = next_PC + instSize; 1062 1063 thread->setNextPC(thread->readNextNPC()); 1064 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 1065#endif |
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1054 } else { 1055 // We shouldn't be in an icache miss and also have a fault (an ITB 1056 // miss) 1057 if (fetchStatus[tid] == IcacheWaitResponse) { 1058 panic("Fetch should have exited prior to this!"); 1059 } 1060 1061 // Send the fault to commit. This thread will not do anything --- 26 unchanged lines hidden (view full) --- 1088 toDecode->insts[numInst] = instruction; 1089 toDecode->size++; 1090 1091 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1092 1093 fetchStatus[tid] = TrapPending; 1094 status_change = true; 1095 | 1066 } else { 1067 // We shouldn't be in an icache miss and also have a fault (an ITB 1068 // miss) 1069 if (fetchStatus[tid] == IcacheWaitResponse) { 1070 panic("Fetch should have exited prior to this!"); 1071 } 1072 1073 // Send the fault to commit. This thread will not do anything --- 26 unchanged lines hidden (view full) --- 1100 toDecode->insts[numInst] = instruction; 1101 toDecode->size++; 1102 1103 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1104 1105 fetchStatus[tid] = TrapPending; 1106 status_change = true; 1107 |
1096 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); | 1108 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); |
1097#else // !FULL_SYSTEM | 1109#else // !FULL_SYSTEM |
1098 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); | 1110 warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); |
1099#endif // FULL_SYSTEM 1100 } 1101} 1102 1103template<class Impl> 1104void 1105DefaultFetch<Impl>::recvRetry() 1106{ --- 152 unchanged lines hidden (view full) --- 1259 return -1; 1260} 1261 1262template<class Impl> 1263int 1264DefaultFetch<Impl>::branchCount() 1265{ 1266 list<unsigned>::iterator threads = (*activeThreads).begin(); | 1111#endif // FULL_SYSTEM 1112 } 1113} 1114 1115template<class Impl> 1116void 1117DefaultFetch<Impl>::recvRetry() 1118{ --- 152 unchanged lines hidden (view full) --- 1271 return -1; 1272} 1273 1274template<class Impl> 1275int 1276DefaultFetch<Impl>::branchCount() 1277{ 1278 list<unsigned>::iterator threads = (*activeThreads).begin(); |
1267 | 1279 warn("Branch Count Fetch policy unimplemented\n"); |
1268 return *threads; 1269} | 1280 return *threads; 1281} |