fetch_impl.hh (2727:91e17c7ee622) fetch_impl.hh (2733:e0eac8fc5774)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "config/use_checker.hh"
32
31#include "arch/isa_traits.hh"
32#include "arch/utility.hh"
33#include "cpu/checker/cpu.hh"
34#include "cpu/exetrace.hh"
35#include "cpu/o3/fetch.hh"
36#include "mem/packet.hh"
37#include "mem/request.hh"
38#include "sim/byteswap.hh"

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263 .flags(Stats::total);
264 fetchRate = fetchedInsts / cpu->numCycles;
265
266 branchPred.regStats();
267}
268
269template<class Impl>
270void
33#include "arch/isa_traits.hh"
34#include "arch/utility.hh"
35#include "cpu/checker/cpu.hh"
36#include "cpu/exetrace.hh"
37#include "cpu/o3/fetch.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40#include "sim/byteswap.hh"

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265 .flags(Stats::total);
266 fetchRate = fetchedInsts / cpu->numCycles;
267
268 branchPred.regStats();
269}
270
271template<class Impl>
272void
271DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr)
273DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
272{
273 DPRINTF(Fetch, "Setting the CPU pointer.\n");
274 cpu = cpu_ptr;
275
276 // Name is finally available, so create the port.
277 icachePort = new IcachePort(this);
278
279 Port *mem_dport = mem->getPort("");
280 icachePort->setPeer(mem_dport);
281 mem_dport->setPeer(icachePort);
282
274{
275 DPRINTF(Fetch, "Setting the CPU pointer.\n");
276 cpu = cpu_ptr;
277
278 // Name is finally available, so create the port.
279 icachePort = new IcachePort(this);
280
281 Port *mem_dport = mem->getPort("");
282 icachePort->setPeer(mem_dport);
283 mem_dport->setPeer(icachePort);
284
285#if USE_CHECKER
283 if (cpu->checker) {
284 cpu->checker->setIcachePort(icachePort);
285 }
286 if (cpu->checker) {
287 cpu->checker->setIcachePort(icachePort);
288 }
289#endif
286
287 // Fetch needs to start fetching instructions at the very beginning,
288 // so it must start up in active state.
289 switchToActive();
290}
291
292template<class Impl>
293void

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425
426template <class Impl>
427inline void
428DefaultFetch<Impl>::switchToActive()
429{
430 if (_status == Inactive) {
431 DPRINTF(Activity, "Activating stage.\n");
432
290
291 // Fetch needs to start fetching instructions at the very beginning,
292 // so it must start up in active state.
293 switchToActive();
294}
295
296template<class Impl>
297void

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429
430template <class Impl>
431inline void
432DefaultFetch<Impl>::switchToActive()
433{
434 if (_status == Inactive) {
435 DPRINTF(Activity, "Activating stage.\n");
436
433 cpu->activateStage(FullCPU::FetchIdx);
437 cpu->activateStage(O3CPU::FetchIdx);
434
435 _status = Active;
436 }
437}
438
439template <class Impl>
440inline void
441DefaultFetch<Impl>::switchToInactive()
442{
443 if (_status == Active) {
444 DPRINTF(Activity, "Deactivating stage.\n");
445
438
439 _status = Active;
440 }
441}
442
443template <class Impl>
444inline void
445DefaultFetch<Impl>::switchToInactive()
446{
447 if (_status == Active) {
448 DPRINTF(Activity, "Deactivating stage.\n");
449
446 cpu->deactivateStage(FullCPU::FetchIdx);
450 cpu->deactivateStage(O3CPU::FetchIdx);
447
448 _status = Inactive;
449 }
450}
451
452template <class Impl>
453bool
454DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)

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657 if (_status == Inactive) {
658 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
659
660 if (fetchStatus[tid] == IcacheAccessComplete) {
661 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
662 "completion\n",tid);
663 }
664
451
452 _status = Inactive;
453 }
454}
455
456template <class Impl>
457bool
458DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)

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661 if (_status == Inactive) {
662 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
663
664 if (fetchStatus[tid] == IcacheAccessComplete) {
665 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
666 "completion\n",tid);
667 }
668
665 cpu->activateStage(FullCPU::FetchIdx);
669 cpu->activateStage(O3CPU::FetchIdx);
666 }
667
668 return Active;
669 }
670 }
671
672 // Stage is switching from active to inactive, notify CPU of it.
673 if (_status == Active) {
674 DPRINTF(Activity, "Deactivating stage.\n");
675
670 }
671
672 return Active;
673 }
674 }
675
676 // Stage is switching from active to inactive, notify CPU of it.
677 if (_status == Active) {
678 DPRINTF(Activity, "Deactivating stage.\n");
679
676 cpu->deactivateStage(FullCPU::FetchIdx);
680 cpu->deactivateStage(O3CPU::FetchIdx);
677 }
678
679 return Inactive;
680}
681
682template <class Impl>
683void
684DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)

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682
683 return Inactive;
684}
685
686template <class Impl>
687void
688DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)

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