fetch_impl.hh (2696:30b38e36ff54) fetch_impl.hh (2698:d5f35d41e017)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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317{
318 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
319 fetchQueue = fq_ptr;
320
321 // Create wire to write information to proper place in fetch queue.
322 toDecode = fetchQueue->getWire(0);
323}
324
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 308 unchanged lines hidden (view full) ---

317{
318 DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
319 fetchQueue = fq_ptr;
320
321 // Create wire to write information to proper place in fetch queue.
322 toDecode = fetchQueue->getWire(0);
323}
324
325#if 0
326template<class Impl>
327void
325template<class Impl>
326void
328DefaultFetch<Impl>::setPageTable(PageTable *pt_ptr)
329{
330 DPRINTF(Fetch, "Setting the page table pointer.\n");
331#if !FULL_SYSTEM
332 pTable = pt_ptr;
333#endif
334}
335#endif
336
337template<class Impl>
338void
339DefaultFetch<Impl>::initStage()
340{
341 // Setup PC and nextPC with initial state.
342 for (int tid = 0; tid < numThreads; tid++) {
343 PC[tid] = cpu->readPC(tid);
344 nextPC[tid] = cpu->readNextPC(tid);
345 }
346}

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376
377 // Only switch to IcacheAccessComplete if we're not stalled as well.
378 if (checkStall(tid)) {
379 fetchStatus[tid] = Blocked;
380 } else {
381 fetchStatus[tid] = IcacheAccessComplete;
382 }
383
327DefaultFetch<Impl>::initStage()
328{
329 // Setup PC and nextPC with initial state.
330 for (int tid = 0; tid < numThreads; tid++) {
331 PC[tid] = cpu->readPC(tid);
332 nextPC[tid] = cpu->readNextPC(tid);
333 }
334}

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364
365 // Only switch to IcacheAccessComplete if we're not stalled as well.
366 if (checkStall(tid)) {
367 fetchStatus[tid] = Blocked;
368 } else {
369 fetchStatus[tid] = IcacheAccessComplete;
370 }
371
384// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
385
386 // Reset the mem req to NULL.
387 delete pkt->req;
388 delete pkt;
389 memReq[tid] = NULL;
390}
391
392template <class Impl>
393void

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589
590 PC[tid] = new_PC;
591 nextPC[tid] = new_PC + instSize;
592
593 // Clear the icache miss if it's outstanding.
594 if (fetchStatus[tid] == IcacheWaitResponse) {
595 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
596 tid);
372 // Reset the mem req to NULL.
373 delete pkt->req;
374 delete pkt;
375 memReq[tid] = NULL;
376}
377
378template <class Impl>
379void

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575
576 PC[tid] = new_PC;
577 nextPC[tid] = new_PC + instSize;
578
579 // Clear the icache miss if it's outstanding.
580 if (fetchStatus[tid] == IcacheWaitResponse) {
581 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
582 tid);
597 // Should I delete this here or when it comes back from the cache?
598// delete memReq[tid];
599 memReq[tid] = NULL;
600 }
601
602 // Get rid of the retrying packet if it was from this thread.
603 if (retryTid == tid) {
604 assert(cacheBlocked);
605 cacheBlocked = false;
606 retryTid = -1;

--- 671 unchanged lines hidden --- 		583 memReq[tid] = NULL;
584 }
585
586 // Get rid of the retrying packet if it was from this thread.
587 if (retryTid == tid) {
588 assert(cacheBlocked);
589 cacheBlocked = false;
590 retryTid = -1;

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