fetch_impl.hh (2690:f4337c0d9e6f) fetch_impl.hh (2696:30b38e36ff54)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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83 fetch->processCacheCompletion(pkt);
84 return true;
85}
86
87template<class Impl>
88void
89DefaultFetch<Impl>::IcachePort::recvRetry()
90{
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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83 fetch->processCacheCompletion(pkt);
84 return true;
85}
86
87template<class Impl>
88void
89DefaultFetch<Impl>::IcachePort::recvRetry()
90{
91 panic("DefaultFetch doesn't support retry yet.");
92 // we shouldn't get a retry unless we have a packet that we're
93 // waiting to transmit
94/*
95 assert(cpu->dcache_pkt != NULL);
96 assert(cpu->_status == DcacheRetry);
97 Packet *tmp = cpu->dcache_pkt;
98 if (sendTiming(tmp)) {
99 cpu->_status = DcacheWaitResponse;
100 cpu->dcache_pkt = NULL;
101 }
102*/
91 fetch->recvRetry();
103}
104
105template<class Impl>
106DefaultFetch<Impl>::DefaultFetch(Params *params)
107 : mem(params->mem),
108 branchPred(params),
109 decodeToFetchDelay(params->decodeToFetchDelay),
110 renameToFetchDelay(params->renameToFetchDelay),
111 iewToFetchDelay(params->iewToFetchDelay),
112 commitToFetchDelay(params->commitToFetchDelay),
113 fetchWidth(params->fetchWidth),
92}
93
94template<class Impl>
95DefaultFetch<Impl>::DefaultFetch(Params *params)
96 : mem(params->mem),
97 branchPred(params),
98 decodeToFetchDelay(params->decodeToFetchDelay),
99 renameToFetchDelay(params->renameToFetchDelay),
100 iewToFetchDelay(params->iewToFetchDelay),
101 commitToFetchDelay(params->commitToFetchDelay),
102 fetchWidth(params->fetchWidth),
103 cacheBlocked(false),
104 retryPkt(NULL),
105 retryTid(-1),
114 numThreads(params->numberOfThreads),
115 numFetchingThreads(params->smtNumFetchingThreads),
116 interruptPending(false),
117 switchedOut(false)
118{
119 if (numThreads > Impl::MaxThreads)
120 fatal("numThreads is not a valid value\n");
121

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505
506#if FULL_SYSTEM
507 // Flag to say whether or not address is physical addr.
508 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
509#else
510 unsigned flags = 0;
511#endif // FULL_SYSTEM
512
106 numThreads(params->numberOfThreads),
107 numFetchingThreads(params->smtNumFetchingThreads),
108 interruptPending(false),
109 switchedOut(false)
110{
111 if (numThreads > Impl::MaxThreads)
112 fatal("numThreads is not a valid value\n");
113

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497
498#if FULL_SYSTEM
499 // Flag to say whether or not address is physical addr.
500 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
501#else
502 unsigned flags = 0;
503#endif // FULL_SYSTEM
504
513 if (interruptPending && flags == 0 || switchedOut) {
514 // Hold off fetch from getting new instructions while an interrupt
515 // is pending.
505 if (cacheBlocked || (interruptPending && flags == 0) || switchedOut) {
506 // Hold off fetch from getting new instructions when:
507 // Cache is blocked, or
508 // while an interrupt is pending and we're not in PAL mode, or
509 // fetch is switched out.
516 return false;
517 }
518
519 // Align the fetch PC so it's at the start of a cache block.
520 fetch_PC = icacheBlockAlignPC(fetch_PC);
521
522 // Setup the memReq to do a read of the first instruction's address.
523 // Set the appropriate read size and flags as well.
524 // Build request here.
525 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
526 fetch_PC, cpu->readCpuId(), tid);
527
528 memReq[tid] = mem_req;
529
530 // Translate the instruction request.
510 return false;
511 }
512
513 // Align the fetch PC so it's at the start of a cache block.
514 fetch_PC = icacheBlockAlignPC(fetch_PC);
515
516 // Setup the memReq to do a read of the first instruction's address.
517 // Set the appropriate read size and flags as well.
518 // Build request here.
519 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
520 fetch_PC, cpu->readCpuId(), tid);
521
522 memReq[tid] = mem_req;
523
524 // Translate the instruction request.
531//#if FULL_SYSTEM
532 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
525 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
533//#else
534// fault = pTable->translate(memReq[tid]);
535//#endif
536
537 // In the case of faults, the fetch stage may need to stall and wait
538 // for the ITB miss to be handled.
539
540 // If translation was successful, attempt to read the first
541 // instruction.
542 if (fault == NoFault) {
543#if 0

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558
559 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
560
561 fetchedCacheLines++;
562
563 // Now do the timing access to see whether or not the instruction
564 // exists within the cache.
565 if (!icachePort->sendTiming(data_pkt)) {
526
527 // In the case of faults, the fetch stage may need to stall and wait
528 // for the ITB miss to be handled.
529
530 // If translation was successful, attempt to read the first
531 // instruction.
532 if (fault == NoFault) {
533#if 0

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548
549 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
550
551 fetchedCacheLines++;
552
553 // Now do the timing access to see whether or not the instruction
554 // exists within the cache.
555 if (!icachePort->sendTiming(data_pkt)) {
556 assert(retryPkt == NULL);
557 assert(retryTid == -1);
566 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
558 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
567 ret_fault = NoFault;
559 fetchStatus[tid] = IcacheWaitRetry;
560 retryPkt = data_pkt;
561 retryTid = tid;
562 cacheBlocked = true;
568 return false;
569 }
570
571 DPRINTF(Fetch, "Doing cache access.\n");
572
573 lastIcacheStall[tid] = curTick;
574
575 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "

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599 if (fetchStatus[tid] == IcacheWaitResponse) {
600 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
601 tid);
602 // Should I delete this here or when it comes back from the cache?
603// delete memReq[tid];
604 memReq[tid] = NULL;
605 }
606
563 return false;
564 }
565
566 DPRINTF(Fetch, "Doing cache access.\n");
567
568 lastIcacheStall[tid] = curTick;
569
570 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "

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594 if (fetchStatus[tid] == IcacheWaitResponse) {
595 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
596 tid);
597 // Should I delete this here or when it comes back from the cache?
598// delete memReq[tid];
599 memReq[tid] = NULL;
600 }
601
602 // Get rid of the retrying packet if it was from this thread.
603 if (retryTid == tid) {
604 assert(cacheBlocked);
605 cacheBlocked = false;
606 retryTid = -1;
607 retryPkt = NULL;
608 delete retryPkt->req;
609 delete retryPkt;
610 }
611
607 fetchStatus[tid] = Squashing;
608
609 ++fetchSquashCycles;
610}
611
612template<class Impl>
613void
614DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,

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1098
1099 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1100#else // !FULL_SYSTEM
1101 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1102#endif // FULL_SYSTEM
1103 }
1104}
1105
612 fetchStatus[tid] = Squashing;
613
614 ++fetchSquashCycles;
615}
616
617template<class Impl>
618void
619DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,

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1103
1104 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1105#else // !FULL_SYSTEM
1106 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1107#endif // FULL_SYSTEM
1108 }
1109}
1110
1111template<class Impl>
1112void
1113DefaultFetch<Impl>::recvRetry()
1114{
1115 assert(cacheBlocked);
1116 if (retryPkt != NULL) {
1117 assert(retryTid != -1);
1118 assert(fetchStatus[retryTid] == IcacheWaitRetry);
1106
1119
1120 if (icachePort->sendTiming(retryPkt)) {
1121 fetchStatus[retryTid] = IcacheWaitResponse;
1122 retryPkt = NULL;
1123 retryTid = -1;
1124 cacheBlocked = false;
1125 }
1126 } else {
1127 assert(retryTid == -1);
1128 // Access has been squashed since it was sent out. Just clear
1129 // the cache being blocked.
1130 cacheBlocked = false;
1131 }
1132}
1133
1107///////////////////////////////////////
1108// //
1109// SMT FETCH POLICY MAINTAINED HERE //
1110// //
1111///////////////////////////////////////
1112template<class Impl>
1113int
1114DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)

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1135// //
1136// SMT FETCH POLICY MAINTAINED HERE //
1137// //
1138///////////////////////////////////////
1139template<class Impl>
1140int
1141DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)

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