fetch_impl.hh (2674:6d4afef73a20) fetch_impl.hh (2678:1f86b91dc3bb)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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100 cpu->_status = DcacheWaitResponse;
101 cpu->dcache_pkt = NULL;
102 }
103*/
104}
105
106template<class Impl>
107DefaultFetch<Impl>::DefaultFetch(Params *params)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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100 cpu->_status = DcacheWaitResponse;
101 cpu->dcache_pkt = NULL;
102 }
103*/
104}
105
106template<class Impl>
107DefaultFetch<Impl>::DefaultFetch(Params *params)
108 : branchPred(params),
108 : mem(params->mem),
109 branchPred(params),
109 decodeToFetchDelay(params->decodeToFetchDelay),
110 renameToFetchDelay(params->renameToFetchDelay),
111 iewToFetchDelay(params->iewToFetchDelay),
112 commitToFetchDelay(params->commitToFetchDelay),
113 fetchWidth(params->fetchWidth),
114 numThreads(params->numberOfThreads),
115 numFetchingThreads(params->smtNumFetchingThreads),
110 decodeToFetchDelay(params->decodeToFetchDelay),
111 renameToFetchDelay(params->renameToFetchDelay),
112 iewToFetchDelay(params->iewToFetchDelay),
113 commitToFetchDelay(params->commitToFetchDelay),
114 fetchWidth(params->fetchWidth),
115 numThreads(params->numberOfThreads),
116 numFetchingThreads(params->smtNumFetchingThreads),
116 interruptPending(false)
117 interruptPending(false),
118 switchedOut(false)
117{
118 if (numThreads > Impl::MaxThreads)
119 fatal("numThreads is not a valid value\n");
120
121 DPRINTF(Fetch, "Fetch constructor called\n");
122
123 // Set fetch stage's status to inactive.
124 _status = Inactive;

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156 cacheBlkMask = (cacheBlkSize - 1);
157
158 for (int tid=0; tid < numThreads; tid++) {
159
160 fetchStatus[tid] = Running;
161
162 priorityList.push_back(tid);
163
119{
120 if (numThreads > Impl::MaxThreads)
121 fatal("numThreads is not a valid value\n");
122
123 DPRINTF(Fetch, "Fetch constructor called\n");
124
125 // Set fetch stage's status to inactive.
126 _status = Inactive;

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158 cacheBlkMask = (cacheBlkSize - 1);
159
160 for (int tid=0; tid < numThreads; tid++) {
161
162 fetchStatus[tid] = Running;
163
164 priorityList.push_back(tid);
165
164 memPkt[tid] = NULL;
166 memReq[tid] = NULL;
165
166 // Create space to store a cache line.
167 cacheData[tid] = new uint8_t[cacheBlkSize];
168
169 stalls[tid].decode = 0;
170 stalls[tid].rename = 0;
171 stalls[tid].iew = 0;
172 stalls[tid].commit = 0;

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278DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr)
279{
280 DPRINTF(Fetch, "Setting the CPU pointer.\n");
281 cpu = cpu_ptr;
282
283 // Name is finally available, so create the port.
284 icachePort = new IcachePort(this);
285
167
168 // Create space to store a cache line.
169 cacheData[tid] = new uint8_t[cacheBlkSize];
170
171 stalls[tid].decode = 0;
172 stalls[tid].rename = 0;
173 stalls[tid].iew = 0;
174 stalls[tid].commit = 0;

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280DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr)
281{
282 DPRINTF(Fetch, "Setting the CPU pointer.\n");
283 cpu = cpu_ptr;
284
285 // Name is finally available, so create the port.
286 icachePort = new IcachePort(this);
287
288 Port *mem_dport = mem->getPort("");
289 icachePort->setPeer(mem_dport);
290 mem_dport->setPeer(icachePort);
291
286 // Fetch needs to start fetching instructions at the very beginning,
287 // so it must start up in active state.
288 switchToActive();
289}
290
291template<class Impl>
292void
293DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)

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350{
351 unsigned tid = pkt->req->getThreadNum();
352
353 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
354
355 // Only change the status if it's still waiting on the icache access
356 // to return.
357 if (fetchStatus[tid] != IcacheWaitResponse ||
292 // Fetch needs to start fetching instructions at the very beginning,
293 // so it must start up in active state.
294 switchToActive();
295}
296
297template<class Impl>
298void
299DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)

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356{
357 unsigned tid = pkt->req->getThreadNum();
358
359 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
360
361 // Only change the status if it's still waiting on the icache access
362 // to return.
363 if (fetchStatus[tid] != IcacheWaitResponse ||
358 pkt != memPkt[tid] ||
364 pkt->req != memReq[tid] ||
359 isSwitchedOut()) {
360 ++fetchIcacheSquashes;
365 isSwitchedOut()) {
366 ++fetchIcacheSquashes;
367 delete pkt->req;
361 delete pkt;
368 delete pkt;
369 memReq[tid] = NULL;
362 return;
363 }
364
365 // Wake up the CPU (if it went to sleep and was waiting on this completion
366 // event).
367 cpu->wakeCPU();
368
369 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",

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378 fetchStatus[tid] = IcacheAccessComplete;
379 }
380
381// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
382
383 // Reset the mem req to NULL.
384 delete pkt->req;
385 delete pkt;
370 return;
371 }
372
373 // Wake up the CPU (if it went to sleep and was waiting on this completion
374 // event).
375 cpu->wakeCPU();
376
377 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",

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386 fetchStatus[tid] = IcacheAccessComplete;
387 }
388
389// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
390
391 // Reset the mem req to NULL.
392 delete pkt->req;
393 delete pkt;
386 memPkt[tid] = NULL;
394 memReq[tid] = NULL;
387}
388
389template <class Impl>
390void
391DefaultFetch<Impl>::switchOut()
392{
393 // Fetch is ready to switch out at any time.
394 switchedOut = true;

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509 fetch_PC = icacheBlockAlignPC(fetch_PC);
510
511 // Setup the memReq to do a read of the first instruction's address.
512 // Set the appropriate read size and flags as well.
513 // Build request here.
514 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
515 fetch_PC, cpu->readCpuId(), tid);
516
395}
396
397template <class Impl>
398void
399DefaultFetch<Impl>::switchOut()
400{
401 // Fetch is ready to switch out at any time.
402 switchedOut = true;

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517 fetch_PC = icacheBlockAlignPC(fetch_PC);
518
519 // Setup the memReq to do a read of the first instruction's address.
520 // Set the appropriate read size and flags as well.
521 // Build request here.
522 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
523 fetch_PC, cpu->readCpuId(), tid);
524
517 memPkt[tid] = NULL;
525 memReq[tid] = mem_req;
518
519 // Translate the instruction request.
520//#if FULL_SYSTEM
521 fault = cpu->translateInstReq(mem_req);
522//#else
523// fault = pTable->translate(memReq[tid]);
524//#endif
525

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560 DPRINTF(Fetch, "Doing cache access.\n");
561
562 lastIcacheStall[tid] = curTick;
563
564 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
565 "response.\n", tid);
566
567 fetchStatus[tid] = IcacheWaitResponse;
526
527 // Translate the instruction request.
528//#if FULL_SYSTEM
529 fault = cpu->translateInstReq(mem_req);
530//#else
531// fault = pTable->translate(memReq[tid]);
532//#endif
533

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568 DPRINTF(Fetch, "Doing cache access.\n");
569
570 lastIcacheStall[tid] = curTick;
571
572 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
573 "response.\n", tid);
574
575 fetchStatus[tid] = IcacheWaitResponse;
576 } else {
577 delete mem_req;
578 memReq[tid] = NULL;
568 }
569
570 ret_fault = fault;
571 return true;
572}
573
574template <class Impl>
575inline void

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580
581 PC[tid] = new_PC;
582 nextPC[tid] = new_PC + instSize;
583
584 // Clear the icache miss if it's outstanding.
585 if (fetchStatus[tid] == IcacheWaitResponse) {
586 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
587 tid);
579 }
580
581 ret_fault = fault;
582 return true;
583}
584
585template <class Impl>
586inline void

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591
592 PC[tid] = new_PC;
593 nextPC[tid] = new_PC + instSize;
594
595 // Clear the icache miss if it's outstanding.
596 if (fetchStatus[tid] == IcacheWaitResponse) {
597 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
598 tid);
588 delete memPkt[tid];
589 memPkt[tid] = NULL;
599 // Should I delete this here or when it comes back from the cache?
600// delete memReq[tid];
601 memReq[tid] = NULL;
590 }
591
592 fetchStatus[tid] = Squashing;
593
594 ++fetchSquashCycles;
595}
596
597template<class Impl>

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1078
1079 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1080
1081 fetchStatus[tid] = TrapPending;
1082 status_change = true;
1083
1084 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1085#else // !FULL_SYSTEM
602 }
603
604 fetchStatus[tid] = Squashing;
605
606 ++fetchSquashCycles;
607}
608
609template<class Impl>

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1090
1091 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1092
1093 fetchStatus[tid] = TrapPending;
1094 status_change = true;
1095
1096 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1097#else // !FULL_SYSTEM
1086 fatal("fault (%d) detected @ PC %08p", fault, PC[tid]);
1098 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1087#endif // FULL_SYSTEM
1088 }
1089}
1090
1091
1092///////////////////////////////////////
1093// //
1094// SMT FETCH POLICY MAINTAINED HERE //

--- 141 unchanged lines hidden --- 		1099#endif // FULL_SYSTEM
1100 }
1101}
1102
1103
1104///////////////////////////////////////
1105// //
1106// SMT FETCH POLICY MAINTAINED HERE //

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