fetch_impl.hh (2654:9559cfa91b9d) | fetch_impl.hh (2665:a124942bacb8) |
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1/* | 1/* |
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan | 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Kevin Lim |
|
27 */ 28 | 29 */ 30 |
31// Remove this later; used only for debugging. 32#define OPCODE(X) (X >> 26) & 0x3f 33 |
|
29#include "arch/isa_traits.hh" | 34#include "arch/isa_traits.hh" |
35#include "sim/byteswap.hh" |
|
30#include "cpu/exetrace.hh" | 36#include "cpu/exetrace.hh" |
31#include "cpu/o3/fetch.hh" | |
32#include "mem/base_mem.hh" 33#include "mem/mem_interface.hh" 34#include "mem/mem_req.hh" | 37#include "mem/base_mem.hh" 38#include "mem/mem_interface.hh" 39#include "mem/mem_req.hh" |
35#include "sim/byteswap.hh" | 40#include "cpu/o3/fetch.hh" 41 |
36#include "sim/root.hh" 37 | 42#include "sim/root.hh" 43 |
38#if FULL_SYSTEM 39#include "arch/tlb.hh" 40#include "arch/vtophys.hh" 41#include "base/remote_gdb.hh" 42#include "mem/functional/memory_control.hh" 43#include "mem/functional/physical.hh" 44#include "sim/system.hh" 45#else // !FULL_SYSTEM 46#include "mem/functional/functional.hh" 47#endif // FULL_SYSTEM 48 49#include <algorithm> 50 51using namespace std; 52 | |
53template<class Impl> | 44template<class Impl> |
54DefaultFetch<Impl>::CacheCompletionEvent::CacheCompletionEvent(MemReqPtr &_req, 55 DefaultFetch *_fetch) 56 : Event(&mainEventQueue, Delayed_Writeback_Pri), 57 req(_req), | 45SimpleFetch<Impl>::CacheCompletionEvent 46::CacheCompletionEvent(SimpleFetch *_fetch) 47 : Event(&mainEventQueue), |
58 fetch(_fetch) 59{ | 48 fetch(_fetch) 49{ |
60 this->setFlags(Event::AutoDelete); | |
61} 62 63template<class Impl> 64void | 50} 51 52template<class Impl> 53void |
65DefaultFetch<Impl>::CacheCompletionEvent::process() | 54SimpleFetch<Impl>::CacheCompletionEvent::process() |
66{ | 55{ |
67 fetch->processCacheCompletion(req); | 56 fetch->processCacheCompletion(); |
68} 69 70template<class Impl> 71const char * | 57} 58 59template<class Impl> 60const char * |
72DefaultFetch<Impl>::CacheCompletionEvent::description() | 61SimpleFetch<Impl>::CacheCompletionEvent::description() |
73{ | 62{ |
74 return "DefaultFetch cache completion event"; | 63 return "SimpleFetch cache completion event"; |
75} 76 77template<class Impl> | 64} 65 66template<class Impl> |
78DefaultFetch<Impl>::DefaultFetch(Params *params) 79 : icacheInterface(params->icacheInterface), | 67SimpleFetch<Impl>::SimpleFetch(Params ¶ms) 68 : icacheInterface(params.icacheInterface), |
80 branchPred(params), | 69 branchPred(params), |
81 decodeToFetchDelay(params->decodeToFetchDelay), 82 renameToFetchDelay(params->renameToFetchDelay), 83 iewToFetchDelay(params->iewToFetchDelay), 84 commitToFetchDelay(params->commitToFetchDelay), 85 fetchWidth(params->fetchWidth), 86 numThreads(params->numberOfThreads), 87 numFetchingThreads(params->smtNumFetchingThreads), 88 interruptPending(false) | 70 decodeToFetchDelay(params.decodeToFetchDelay), 71 renameToFetchDelay(params.renameToFetchDelay), 72 iewToFetchDelay(params.iewToFetchDelay), 73 commitToFetchDelay(params.commitToFetchDelay), 74 fetchWidth(params.fetchWidth) |
89{ | 75{ |
90 if (numThreads > Impl::MaxThreads) 91 fatal("numThreads is not a valid value\n"); | 76 DPRINTF(Fetch, "Fetch: Fetch constructor called\n"); |
92 | 77 |
93 DPRINTF(Fetch, "Fetch constructor called\n"); | 78 // Set status to idle. 79 _status = Idle; |
94 | 80 |
95 // Set fetch stage's status to inactive. 96 _status = Inactive; | 81 // Create a new memory request. 82 memReq = new MemReq(); 83 // Not sure of this parameter. I think it should be based on the 84 // thread number. 85#if !FULL_SYSTEM 86 memReq->asid = 0; 87#else 88 memReq->asid = 0; 89#endif // FULL_SYSTEM 90 memReq->data = new uint8_t[64]; |
97 | 91 |
98 string policy = params->smtFetchPolicy; 99 100 // Convert string to lowercase 101 std::transform(policy.begin(), policy.end(), policy.begin(), 102 (int(*)(int)) tolower); 103 104 // Figure out fetch policy 105 if (policy == "singlethread") { 106 fetchPolicy = SingleThread; 107 } else if (policy == "roundrobin") { 108 fetchPolicy = RoundRobin; 109 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 110 } else if (policy == "branch") { 111 fetchPolicy = Branch; 112 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 113 } else if (policy == "iqcount") { 114 fetchPolicy = IQ; 115 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 116 } else if (policy == "lsqcount") { 117 fetchPolicy = LSQ; 118 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 119 } else { 120 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 121 " RoundRobin,LSQcount,IQcount}\n"); 122 } 123 | |
124 // Size of cache block. 125 cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64; 126 127 // Create mask to get rid of offset bits. 128 cacheBlkMask = (cacheBlkSize - 1); 129 | 92 // Size of cache block. 93 cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64; 94 95 // Create mask to get rid of offset bits. 96 cacheBlkMask = (cacheBlkSize - 1); 97 |
130 for (int tid=0; tid < numThreads; tid++) { 131 132 fetchStatus[tid] = Running; 133 134 priorityList.push_back(tid); 135 136 // Create a new memory request. 137 memReq[tid] = NULL; 138 139 // Create space to store a cache line. 140 cacheData[tid] = new uint8_t[cacheBlkSize]; 141 142 stalls[tid].decode = 0; 143 stalls[tid].rename = 0; 144 stalls[tid].iew = 0; 145 stalls[tid].commit = 0; 146 } 147 | |
148 // Get the size of an instruction. 149 instSize = sizeof(MachInst); | 98 // Get the size of an instruction. 99 instSize = sizeof(MachInst); |
150} | |
151 | 100 |
152template <class Impl> 153std::string 154DefaultFetch<Impl>::name() const 155{ 156 return cpu->name() + ".fetch"; | 101 // Create space to store a cache line. 102 cacheData = new uint8_t[cacheBlkSize]; |
157} 158 159template <class Impl> 160void | 103} 104 105template <class Impl> 106void |
161DefaultFetch<Impl>::regStats() | 107SimpleFetch<Impl>::regStats() |
162{ 163 icacheStallCycles | 108{ 109 icacheStallCycles |
164 .name(name() + ".FETCH:icacheStallCycles") | 110 .name(name() + ".icacheStallCycles") |
165 .desc("Number of cycles fetch is stalled on an Icache miss") 166 .prereq(icacheStallCycles); 167 168 fetchedInsts | 111 .desc("Number of cycles fetch is stalled on an Icache miss") 112 .prereq(icacheStallCycles); 113 114 fetchedInsts |
169 .name(name() + ".FETCH:Insts") | 115 .name(name() + ".fetchedInsts") |
170 .desc("Number of instructions fetch has processed") 171 .prereq(fetchedInsts); | 116 .desc("Number of instructions fetch has processed") 117 .prereq(fetchedInsts); |
172 173 fetchedBranches 174 .name(name() + ".FETCH:Branches") 175 .desc("Number of branches that fetch encountered") 176 .prereq(fetchedBranches); 177 | |
178 predictedBranches | 118 predictedBranches |
179 .name(name() + ".FETCH:predictedBranches") | 119 .name(name() + ".predictedBranches") |
180 .desc("Number of branches that fetch has predicted taken") 181 .prereq(predictedBranches); | 120 .desc("Number of branches that fetch has predicted taken") 121 .prereq(predictedBranches); |
182 | |
183 fetchCycles | 122 fetchCycles |
184 .name(name() + ".FETCH:Cycles") | 123 .name(name() + ".fetchCycles") |
185 .desc("Number of cycles fetch has run and was not squashing or" 186 " blocked") 187 .prereq(fetchCycles); | 124 .desc("Number of cycles fetch has run and was not squashing or" 125 " blocked") 126 .prereq(fetchCycles); |
188 | |
189 fetchSquashCycles | 127 fetchSquashCycles |
190 .name(name() + ".FETCH:SquashCycles") | 128 .name(name() + ".fetchSquashCycles") |
191 .desc("Number of cycles fetch has spent squashing") 192 .prereq(fetchSquashCycles); | 129 .desc("Number of cycles fetch has spent squashing") 130 .prereq(fetchSquashCycles); |
193 194 fetchIdleCycles 195 .name(name() + ".FETCH:IdleCycles") 196 .desc("Number of cycles fetch was idle") 197 .prereq(fetchIdleCycles); 198 | |
199 fetchBlockedCycles | 131 fetchBlockedCycles |
200 .name(name() + ".FETCH:BlockedCycles") | 132 .name(name() + ".fetchBlockedCycles") |
201 .desc("Number of cycles fetch has spent blocked") 202 .prereq(fetchBlockedCycles); | 133 .desc("Number of cycles fetch has spent blocked") 134 .prereq(fetchBlockedCycles); |
203 | |
204 fetchedCacheLines | 135 fetchedCacheLines |
205 .name(name() + ".FETCH:CacheLines") | 136 .name(name() + ".fetchedCacheLines") |
206 .desc("Number of cache lines fetched") 207 .prereq(fetchedCacheLines); 208 | 137 .desc("Number of cache lines fetched") 138 .prereq(fetchedCacheLines); 139 |
209 fetchMiscStallCycles 210 .name(name() + ".FETCH:MiscStallCycles") 211 .desc("Number of cycles fetch has spent waiting on interrupts, or " 212 "bad addresses, or out of MSHRs") 213 .prereq(fetchMiscStallCycles); 214 215 fetchIcacheSquashes 216 .name(name() + ".FETCH:IcacheSquashes") 217 .desc("Number of outstanding Icache misses that were squashed") 218 .prereq(fetchIcacheSquashes); 219 220 fetchNisnDist | 140 fetch_nisn_dist |
221 .init(/* base value */ 0, 222 /* last value */ fetchWidth, 223 /* bucket size */ 1) | 141 .init(/* base value */ 0, 142 /* last value */ fetchWidth, 143 /* bucket size */ 1) |
224 .name(name() + ".FETCH:rateDist") | 144 .name(name() + ".FETCH:rate_dist") |
225 .desc("Number of instructions fetched each cycle (Total)") | 145 .desc("Number of instructions fetched each cycle (Total)") |
226 .flags(Stats::pdf); | 146 .flags(Stats::pdf) 147 ; |
227 | 148 |
228 idleRate 229 .name(name() + ".FETCH:idleRate") 230 .desc("Percent of cycles fetch was idle") 231 .prereq(idleRate); 232 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 233 234 branchRate 235 .name(name() + ".FETCH:branchRate") 236 .desc("Number of branch fetches per cycle") 237 .flags(Stats::total); 238 branchRate = predictedBranches / cpu->numCycles; 239 240 fetchRate 241 .name(name() + ".FETCH:rate") 242 .desc("Number of inst fetches per cycle") 243 .flags(Stats::total); 244 fetchRate = fetchedInsts / cpu->numCycles; 245 | |
246 branchPred.regStats(); 247} 248 249template<class Impl> 250void | 149 branchPred.regStats(); 150} 151 152template<class Impl> 153void |
251DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr) | 154SimpleFetch<Impl>::setCPU(FullCPU *cpu_ptr) |
252{ | 155{ |
253 DPRINTF(Fetch, "Setting the CPU pointer.\n"); | 156 DPRINTF(Fetch, "Fetch: Setting the CPU pointer.\n"); |
254 cpu = cpu_ptr; | 157 cpu = cpu_ptr; |
255 256 // Fetch needs to start fetching instructions at the very beginning, 257 // so it must start up in active state. 258 switchToActive(); | 158 // This line will be removed eventually. 159 memReq->xc = cpu->xcBase(); |
259} 260 261template<class Impl> 262void | 160} 161 162template<class Impl> 163void |
263DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) | 164SimpleFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) |
264{ | 165{ |
265 DPRINTF(Fetch, "Setting the time buffer pointer.\n"); | 166 DPRINTF(Fetch, "Fetch: Setting the time buffer pointer.\n"); |
266 timeBuffer = time_buffer; 267 268 // Create wires to get information from proper places in time buffer. 269 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 270 fromRename = timeBuffer->getWire(-renameToFetchDelay); 271 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 272 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 273} 274 275template<class Impl> 276void | 167 timeBuffer = time_buffer; 168 169 // Create wires to get information from proper places in time buffer. 170 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 171 fromRename = timeBuffer->getWire(-renameToFetchDelay); 172 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 173 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 174} 175 176template<class Impl> 177void |
277DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr) | 178SimpleFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) |
278{ | 179{ |
279 DPRINTF(Fetch, "Setting active threads list pointer.\n"); 280 activeThreads = at_ptr; 281} 282 283template<class Impl> 284void 285DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 286{ 287 DPRINTF(Fetch, "Setting the fetch queue pointer.\n"); | 180 DPRINTF(Fetch, "Fetch: Setting the fetch queue pointer.\n"); |
288 fetchQueue = fq_ptr; 289 290 // Create wire to write information to proper place in fetch queue. 291 toDecode = fetchQueue->getWire(0); 292} 293 | 181 fetchQueue = fq_ptr; 182 183 // Create wire to write information to proper place in fetch queue. 184 toDecode = fetchQueue->getWire(0); 185} 186 |
294#if 0 | |
295template<class Impl> 296void | 187template<class Impl> 188void |
297DefaultFetch<Impl>::setPageTable(PageTable *pt_ptr) | 189SimpleFetch<Impl>::processCacheCompletion() |
298{ | 190{ |
299 DPRINTF(Fetch, "Setting the page table pointer.\n"); 300#if !FULL_SYSTEM 301 pTable = pt_ptr; 302#endif 303} 304#endif | 191 DPRINTF(Fetch, "Fetch: Waking up from cache miss.\n"); |
305 | 192 |
306template<class Impl> 307void 308DefaultFetch<Impl>::initStage() 309{ 310 for (int tid = 0; tid < numThreads; tid++) { 311 PC[tid] = cpu->readPC(tid); 312 nextPC[tid] = cpu->readNextPC(tid); 313 } 314} 315 316template<class Impl> 317void 318DefaultFetch<Impl>::processCacheCompletion(MemReqPtr &req) 319{ 320 unsigned tid = req->thread_num; 321 322 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 323 | |
324 // Only change the status if it's still waiting on the icache access 325 // to return. 326 // Can keep track of how many cache accesses go unused due to 327 // misspeculation here. | 193 // Only change the status if it's still waiting on the icache access 194 // to return. 195 // Can keep track of how many cache accesses go unused due to 196 // misspeculation here. |
328 if (fetchStatus[tid] != IcacheMissStall || 329 req != memReq[tid] || 330 isSwitchedOut()) { 331 ++fetchIcacheSquashes; 332 return; 333 } 334 335 // Wake up the CPU (if it went to sleep and was waiting on this completion 336 // event). 337 cpu->wakeCPU(); 338 339 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 340 tid); 341 342 switchToActive(); 343 344 // Only switch to IcacheMissComplete if we're not stalled as well. 345 if (checkStall(tid)) { 346 fetchStatus[tid] = Blocked; 347 } else { 348 fetchStatus[tid] = IcacheMissComplete; 349 } 350 351// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size); 352 353 // Reset the mem req to NULL. 354 memReq[tid] = NULL; | 197 if (_status == IcacheMissStall) 198 _status = IcacheMissComplete; |
355} 356 357template <class Impl> | 199} 200 201template <class Impl> |
358void 359DefaultFetch<Impl>::switchOut() 360{ 361 switchedOut = true; 362 cpu->signalSwitched(); 363} 364 365template <class Impl> 366void 367DefaultFetch<Impl>::doSwitchOut() 368{ 369 branchPred.switchOut(); 370} 371 372template <class Impl> 373void 374DefaultFetch<Impl>::takeOverFrom() 375{ 376 // Reset all state 377 for (int i = 0; i < Impl::MaxThreads; ++i) { 378 stalls[i].decode = 0; 379 stalls[i].rename = 0; 380 stalls[i].iew = 0; 381 stalls[i].commit = 0; 382 PC[i] = cpu->readPC(i); 383 nextPC[i] = cpu->readNextPC(i); 384 fetchStatus[i] = Running; 385 } 386 numInst = 0; 387 wroteToTimeBuffer = false; 388 _status = Inactive; 389 switchedOut = false; 390 branchPred.takeOverFrom(); 391} 392 393template <class Impl> 394void 395DefaultFetch<Impl>::wakeFromQuiesce() 396{ 397 DPRINTF(Fetch, "Waking up from quiesce\n"); 398 // Hopefully this is safe 399 fetchStatus[0] = Running; 400} 401 402template <class Impl> 403inline void 404DefaultFetch<Impl>::switchToActive() 405{ 406 if (_status == Inactive) { 407 DPRINTF(Activity, "Activating stage.\n"); 408 409 cpu->activateStage(FullCPU::FetchIdx); 410 411 _status = Active; 412 } 413} 414 415template <class Impl> 416inline void 417DefaultFetch<Impl>::switchToInactive() 418{ 419 if (_status == Active) { 420 DPRINTF(Activity, "Deactivating stage.\n"); 421 422 cpu->deactivateStage(FullCPU::FetchIdx); 423 424 _status = Inactive; 425 } 426} 427 428template <class Impl> | |
429bool | 202bool |
430DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC) | 203SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC) |
431{ 432 // Do branch prediction check here. 433 // A bit of a misnomer...next_PC is actually the current PC until 434 // this function updates it. 435 bool predict_taken; 436 437 if (!inst->isControl()) { 438 next_PC = next_PC + instSize; 439 inst->setPredTarg(next_PC); 440 return false; 441 } 442 | 204{ 205 // Do branch prediction check here. 206 // A bit of a misnomer...next_PC is actually the current PC until 207 // this function updates it. 208 bool predict_taken; 209 210 if (!inst->isControl()) { 211 next_PC = next_PC + instSize; 212 inst->setPredTarg(next_PC); 213 return false; 214 } 215 |
443 predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber); | 216 predict_taken = branchPred.predict(inst, next_PC); |
444 | 217 |
445 ++fetchedBranches; 446 | |
447 if (predict_taken) { 448 ++predictedBranches; 449 } 450 451 return predict_taken; 452} 453 454template <class Impl> | 218 if (predict_taken) { 219 ++predictedBranches; 220 } 221 222 return predict_taken; 223} 224 225template <class Impl> |
455bool 456DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid) | 226Fault 227SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC) |
457{ | 228{ |
458 Fault fault = NoFault; | 229 // Check if the instruction exists within the cache. 230 // If it does, then proceed on to read the instruction and the rest 231 // of the instructions in the cache line until either the end of the 232 // cache line or a predicted taken branch is encountered. |
459 460#if FULL_SYSTEM 461 // Flag to say whether or not address is physical addr. | 233 234#if FULL_SYSTEM 235 // Flag to say whether or not address is physical addr. |
462 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0; | 236 unsigned flags = cpu->inPalMode() ? PHYSICAL : 0; |
463#else 464 unsigned flags = 0; 465#endif // FULL_SYSTEM 466 | 237#else 238 unsigned flags = 0; 239#endif // FULL_SYSTEM 240 |
467 if (interruptPending && flags == 0 || switchedOut) { 468 // Hold off fetch from getting new instructions while an interrupt 469 // is pending. 470 return false; 471 } | 241 Fault fault = NoFault; |
472 473 // Align the fetch PC so it's at the start of a cache block. 474 fetch_PC = icacheBlockAlignPC(fetch_PC); 475 | 242 243 // Align the fetch PC so it's at the start of a cache block. 244 fetch_PC = icacheBlockAlignPC(fetch_PC); 245 |
476 // Setup the memReq to do a read of the first instruction's address. | 246 // Setup the memReq to do a read of the first isntruction's address. |
477 // Set the appropriate read size and flags as well. | 247 // Set the appropriate read size and flags as well. |
478 memReq[tid] = new MemReq(); | 248 memReq->cmd = Read; 249 memReq->reset(fetch_PC, cacheBlkSize, flags); |
479 | 250 |
480 memReq[tid]->asid = tid; 481 memReq[tid]->thread_num = tid; 482 memReq[tid]->data = new uint8_t[64]; 483 memReq[tid]->xc = cpu->xcBase(tid); 484 memReq[tid]->cmd = Read; 485 memReq[tid]->reset(fetch_PC, cacheBlkSize, flags); 486 | |
487 // Translate the instruction request. | 251 // Translate the instruction request. |
488//#if FULL_SYSTEM 489 fault = cpu->translateInstReq(memReq[tid]); 490//#else 491// fault = pTable->translate(memReq[tid]); 492//#endif | 252 // Should this function be 253 // in the CPU class ? Probably...ITB/DTB should exist within the 254 // CPU. |
493 | 255 |
256 fault = cpu->translateInstReq(memReq); 257 |
|
494 // In the case of faults, the fetch stage may need to stall and wait | 258 // In the case of faults, the fetch stage may need to stall and wait |
495 // for the ITB miss to be handled. | 259 // on what caused the fetch (ITB or Icache miss). |
496 497 // If translation was successful, attempt to read the first 498 // instruction. 499 if (fault == NoFault) { | 260 261 // If translation was successful, attempt to read the first 262 // instruction. 263 if (fault == NoFault) { |
500#if FULL_SYSTEM 501 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) || 502 memReq[tid]->flags & UNCACHEABLE) { 503 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a " 504 "misspeculating path)!", 505 memReq[tid]->paddr); 506 ret_fault = TheISA::genMachineCheckFault(); 507 return false; 508 } 509#endif 510 | |
511 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); | 264 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); |
512 fault = cpu->mem->read(memReq[tid], cacheData[tid]); | 265 fault = cpu->mem->read(memReq, cacheData); |
513 // This read may change when the mem interface changes. 514 | 266 // This read may change when the mem interface changes. 267 |
515 // Now do the timing access to see whether or not the instruction 516 // exists within the cache. 517 if (icacheInterface && !icacheInterface->isBlocked()) { 518 DPRINTF(Fetch, "Doing cache access.\n"); | 268 fetchedCacheLines++; 269 } |
519 | 270 |
520 memReq[tid]->completionEvent = NULL; | 271 // Now do the timing access to see whether or not the instruction 272 // exists within the cache. 273 if (icacheInterface && fault == NoFault) { 274 DPRINTF(Fetch, "Fetch: Doing timing memory access.\n"); 275 memReq->completionEvent = NULL; |
521 | 276 |
522 memReq[tid]->time = curTick; | 277 memReq->time = curTick; |
523 | 278 |
524 MemAccessResult result = icacheInterface->access(memReq[tid]); | 279 MemAccessResult result = icacheInterface->access(memReq); |
525 | 280 |
526 fetchedCacheLines++; | 281 // If the cache missed (in this model functional and timing 282 // memories are different), then schedule an event to wake 283 // up this stage once the cache miss completes. 284 if (result != MA_HIT && icacheInterface->doEvents()) { 285 memReq->completionEvent = new CacheCompletionEvent(this); |
527 | 286 |
528 // If the cache missed, then schedule an event to wake 529 // up this stage once the cache miss completes. 530 // @todo: Possibly allow for longer than 1 cycle cache hits. 531 if (result != MA_HIT && icacheInterface->doEvents()) { | 287 // How does current model work as far as individual 288 // stages scheduling/unscheduling? 289 // Perhaps have only the main CPU scheduled/unscheduled, 290 // and have it choose what stages to run appropriately. |
532 | 291 |
533 memReq[tid]->completionEvent = 534 new CacheCompletionEvent(memReq[tid], this); 535 536 lastIcacheStall[tid] = curTick; 537 538 DPRINTF(Activity, "[tid:%i]: Activity: Stalling due to I-cache " 539 "miss.\n", tid); 540 541 fetchStatus[tid] = IcacheMissStall; 542 } else { 543 DPRINTF(Fetch, "[tid:%i]: I-Cache hit. Doing Instruction " 544 "read.\n", tid); 545 546// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size); 547 } 548 } else { 549 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 550 ret_fault = NoFault; 551 return false; | 292 DPRINTF(Fetch, "Fetch: Stalling due to icache miss.\n"); 293 _status = IcacheMissStall; |
552 } 553 } 554 | 294 } 295 } 296 |
555 ret_fault = fault; 556 return true; | 297 return fault; |
557} 558 559template <class Impl> 560inline void | 298} 299 300template <class Impl> 301inline void |
561DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid) | 302SimpleFetch<Impl>::doSquash(const Addr &new_PC) |
562{ | 303{ |
563 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n", 564 tid, new_PC); | 304 DPRINTF(Fetch, "Fetch: Squashing, setting PC to: %#x.\n", new_PC); |
565 | 305 |
566 PC[tid] = new_PC; 567 nextPC[tid] = new_PC + instSize; | 306 cpu->setNextPC(new_PC + instSize); 307 cpu->setPC(new_PC); |
568 569 // Clear the icache miss if it's outstanding. | 308 309 // Clear the icache miss if it's outstanding. |
570 if (fetchStatus[tid] == IcacheMissStall && icacheInterface) { 571 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 572 tid); 573 memReq[tid] = NULL; | 310 if (_status == IcacheMissStall && icacheInterface) { 311 DPRINTF(Fetch, "Fetch: Squashing outstanding Icache miss.\n"); 312 // @todo: Use an actual thread number here. 313 icacheInterface->squash(0); |
574 } 575 | 314 } 315 |
576 fetchStatus[tid] = Squashing; | 316 _status = Squashing; |
577 578 ++fetchSquashCycles; 579} 580 581template<class Impl> 582void | 317 318 ++fetchSquashCycles; 319} 320 321template<class Impl> 322void |
583DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, 584 const InstSeqNum &seq_num, 585 unsigned tid) | 323SimpleFetch<Impl>::squashFromDecode(const Addr &new_PC, 324 const InstSeqNum &seq_num) |
586{ | 325{ |
587 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); | 326 DPRINTF(Fetch, "Fetch: Squashing from decode.\n"); |
588 | 327 |
589 doSquash(new_PC, tid); | 328 doSquash(new_PC); |
590 591 // Tell the CPU to remove any instructions that are in flight between 592 // fetch and decode. | 329 330 // Tell the CPU to remove any instructions that are in flight between 331 // fetch and decode. |
593 cpu->removeInstsUntil(seq_num, tid); | 332 cpu->removeInstsUntil(seq_num); |
594} 595 | 333} 334 |
596template<class Impl> 597bool 598DefaultFetch<Impl>::checkStall(unsigned tid) const 599{ 600 bool ret_val = false; 601 602 if (cpu->contextSwitch) { 603 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 604 ret_val = true; 605 } else if (stalls[tid].decode) { 606 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 607 ret_val = true; 608 } else if (stalls[tid].rename) { 609 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 610 ret_val = true; 611 } else if (stalls[tid].iew) { 612 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 613 ret_val = true; 614 } else if (stalls[tid].commit) { 615 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 616 ret_val = true; 617 } 618 619 return ret_val; 620} 621 622template<class Impl> 623typename DefaultFetch<Impl>::FetchStatus 624DefaultFetch<Impl>::updateFetchStatus() 625{ 626 //Check Running 627 list<unsigned>::iterator threads = (*activeThreads).begin(); 628 629 while (threads != (*activeThreads).end()) { 630 631 unsigned tid = *threads++; 632 633 if (fetchStatus[tid] == Running || 634 fetchStatus[tid] == Squashing || 635 fetchStatus[tid] == IcacheMissComplete) { 636 637 if (_status == Inactive) { 638 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 639 640 if (fetchStatus[tid] == IcacheMissComplete) { 641 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 642 "completion\n",tid); 643 } 644 645 cpu->activateStage(FullCPU::FetchIdx); 646 } 647 648 return Active; 649 } 650 } 651 652 // Stage is switching from active to inactive, notify CPU of it. 653 if (_status == Active) { 654 DPRINTF(Activity, "Deactivating stage.\n"); 655 656 cpu->deactivateStage(FullCPU::FetchIdx); 657 } 658 659 return Inactive; 660} 661 | |
662template <class Impl> 663void | 335template <class Impl> 336void |
664DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid) | 337SimpleFetch<Impl>::squash(const Addr &new_PC) |
665{ | 338{ |
666 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); | 339 DPRINTF(Fetch, "Fetch: Squash from commit.\n"); |
667 | 340 |
668 doSquash(new_PC, tid); | 341 doSquash(new_PC); |
669 670 // Tell the CPU to remove any instructions that are not in the ROB. | 342 343 // Tell the CPU to remove any instructions that are not in the ROB. |
671 cpu->removeInstsNotInROB(tid); | 344 cpu->removeInstsNotInROB(); |
672} 673 | 345} 346 |
674template <class Impl> | 347template |
675void | 348void |
676DefaultFetch<Impl>::tick() | 349SimpleFetch<Impl>::tick() |
677{ | 350{ |
678 list<unsigned>::iterator threads = (*activeThreads).begin(); 679 bool status_change = false; 680 681 wroteToTimeBuffer = false; 682 683 while (threads != (*activeThreads).end()) { 684 unsigned tid = *threads++; 685 686 // Check the signals for each thread to determine the proper status 687 // for each thread. 688 bool updated_status = checkSignalsAndUpdate(tid); 689 status_change = status_change || updated_status; 690 } 691 692 DPRINTF(Fetch, "Running stage.\n"); 693 694 // Reset the number of the instruction we're fetching. 695 numInst = 0; 696 697 if (fromCommit->commitInfo[0].interruptPending) { 698 interruptPending = true; 699 } 700 if (fromCommit->commitInfo[0].clearInterrupt) { 701 interruptPending = false; 702 } 703 704 for (threadFetched = 0; threadFetched < numFetchingThreads; 705 threadFetched++) { 706 // Fetch each of the actively fetching threads. 707 fetch(status_change); 708 } 709 710 // Record number of instructions fetched this cycle for distribution. 711 fetchNisnDist.sample(numInst); 712 713 if (status_change) { 714 // Change the fetch stage status if there was a status change. 715 _status = updateFetchStatus(); 716 } 717 718 // If there was activity this cycle, inform the CPU of it. 719 if (wroteToTimeBuffer || cpu->contextSwitch) { 720 DPRINTF(Activity, "Activity this cycle.\n"); 721 722 cpu->activityThisCycle(); 723 } 724} 725 726template <class Impl> 727bool 728DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) 729{ 730 // Update the per thread stall statuses. 731 if (fromDecode->decodeBlock[tid]) { 732 stalls[tid].decode = true; 733 } 734 735 if (fromDecode->decodeUnblock[tid]) { 736 assert(stalls[tid].decode); 737 assert(!fromDecode->decodeBlock[tid]); 738 stalls[tid].decode = false; 739 } 740 741 if (fromRename->renameBlock[tid]) { 742 stalls[tid].rename = true; 743 } 744 745 if (fromRename->renameUnblock[tid]) { 746 assert(stalls[tid].rename); 747 assert(!fromRename->renameBlock[tid]); 748 stalls[tid].rename = false; 749 } 750 751 if (fromIEW->iewBlock[tid]) { 752 stalls[tid].iew = true; 753 } 754 755 if (fromIEW->iewUnblock[tid]) { 756 assert(stalls[tid].iew); 757 assert(!fromIEW->iewBlock[tid]); 758 stalls[tid].iew = false; 759 } 760 761 if (fromCommit->commitBlock[tid]) { 762 stalls[tid].commit = true; 763 } 764 765 if (fromCommit->commitUnblock[tid]) { 766 assert(stalls[tid].commit); 767 assert(!fromCommit->commitBlock[tid]); 768 stalls[tid].commit = false; 769 } 770 | |
771 // Check squash signals from commit. | 351 // Check squash signals from commit. |
772 if (fromCommit->commitInfo[tid].squash) { | 352 if (fromCommit->commitInfo.squash) { 353 DPRINTF(Fetch, "Fetch: Squashing instructions due to squash " 354 "from commit.\n"); |
773 | 355 |
774 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 775 "from commit.\n",tid); 776 | |
777 // In any case, squash. | 356 // In any case, squash. |
778 squash(fromCommit->commitInfo[tid].nextPC,tid); | 357 squash(fromCommit->commitInfo.nextPC); |
779 780 // Also check if there's a mispredict that happened. | 358 359 // Also check if there's a mispredict that happened. |
781 if (fromCommit->commitInfo[tid].branchMispredict) { 782 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 783 fromCommit->commitInfo[tid].nextPC, 784 fromCommit->commitInfo[tid].branchTaken, 785 tid); | 360 if (fromCommit->commitInfo.branchMispredict) { 361 branchPred.squash(fromCommit->commitInfo.doneSeqNum, 362 fromCommit->commitInfo.nextPC, 363 fromCommit->commitInfo.branchTaken); |
786 } else { | 364 } else { |
787 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 788 tid); | 365 branchPred.squash(fromCommit->commitInfo.doneSeqNum); |
789 } 790 | 366 } 367 |
791 return true; 792 } else if (fromCommit->commitInfo[tid].doneSeqNum) { | 368 return; 369 } else if (fromCommit->commitInfo.doneSeqNum) { |
793 // Update the branch predictor if it wasn't a squashed instruction | 370 // Update the branch predictor if it wasn't a squashed instruction |
794 // that was broadcasted. 795 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); | 371 // that was braodcasted. 372 branchPred.update(fromCommit->commitInfo.doneSeqNum); |
796 } 797 798 // Check ROB squash signals from commit. | 373 } 374 375 // Check ROB squash signals from commit. |
799 if (fromCommit->commitInfo[tid].robSquashing) { 800 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing Thread %u.\n", tid); | 376 if (fromCommit->commitInfo.robSquashing) { 377 DPRINTF(Fetch, "Fetch: ROB is still squashing.\n"); |
801 802 // Continue to squash. | 378 379 // Continue to squash. |
803 fetchStatus[tid] = Squashing; | 380 _status = Squashing; |
804 | 381 |
805 return true; | 382 ++fetchSquashCycles; 383 return; |
806 } 807 808 // Check squash signals from decode. | 384 } 385 386 // Check squash signals from decode. |
809 if (fromDecode->decodeInfo[tid].squash) { 810 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 811 "from decode.\n",tid); | 387 if (fromDecode->decodeInfo.squash) { 388 DPRINTF(Fetch, "Fetch: Squashing instructions due to squash " 389 "from decode.\n"); |
812 813 // Update the branch predictor. | 390 391 // Update the branch predictor. |
814 if (fromDecode->decodeInfo[tid].branchMispredict) { 815 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 816 fromDecode->decodeInfo[tid].nextPC, 817 fromDecode->decodeInfo[tid].branchTaken, 818 tid); | 392 if (fromDecode->decodeInfo.branchMispredict) { 393 branchPred.squash(fromDecode->decodeInfo.doneSeqNum, 394 fromDecode->decodeInfo.nextPC, 395 fromDecode->decodeInfo.branchTaken); |
819 } else { | 396 } else { |
820 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 821 tid); | 397 branchPred.squash(fromDecode->decodeInfo.doneSeqNum); |
822 } 823 | 398 } 399 |
824 if (fetchStatus[tid] != Squashing) { 825 // Squash unless we're already squashing 826 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 827 fromDecode->decodeInfo[tid].doneSeqNum, 828 tid); 829 830 return true; | 400 if (_status != Squashing) { 401 // Squash unless we're already squashing? 402 squashFromDecode(fromDecode->decodeInfo.nextPC, 403 fromDecode->decodeInfo.doneSeqNum); 404 return; |
831 } 832 } 833 | 405 } 406 } 407 |
834 if (checkStall(tid) && fetchStatus[tid] != IcacheMissStall) { 835 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); | 408 // Check if any of the stall signals are high. 409 if (fromDecode->decodeInfo.stall || 410 fromRename->renameInfo.stall || 411 fromIEW->iewInfo.stall || 412 fromCommit->commitInfo.stall) 413 { 414 // Block stage, regardless of current status. |
836 | 415 |
837 fetchStatus[tid] = Blocked; | 416 DPRINTF(Fetch, "Fetch: Stalling stage.\n"); 417 DPRINTF(Fetch, "Fetch: Statuses: Decode: %i Rename: %i IEW: %i " 418 "Commit: %i\n", 419 fromDecode->decodeInfo.stall, 420 fromRename->renameInfo.stall, 421 fromIEW->iewInfo.stall, 422 fromCommit->commitInfo.stall); |
838 | 423 |
839 return true; | 424 _status = Blocked; 425 426 ++fetchBlockedCycles; 427 return; 428 } else if (_status == Blocked) { 429 // Unblock stage if status is currently blocked and none of the 430 // stall signals are being held high. 431 _status = Running; 432 433 ++fetchBlockedCycles; 434 return; |
840 } 841 | 435 } 436 |
842 if (fetchStatus[tid] == Blocked || 843 fetchStatus[tid] == Squashing) { 844 // Switch status to running if fetch isn't being told to block or 845 // squash this cycle. 846 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 847 tid); | 437 // If fetch has reached this point, then there are no squash signals 438 // still being held high. Check if fetch is in the squashing state; 439 // if so, fetch can switch to running. 440 // Similarly, there are no blocked signals still being held high. 441 // Check if fetch is in the blocked state; if so, fetch can switch to 442 // running. 443 if (_status == Squashing) { 444 DPRINTF(Fetch, "Fetch: Done squashing, switching to running.\n"); |
848 | 445 |
849 fetchStatus[tid] = Running; | 446 // Switch status to running 447 _status = Running; |
850 | 448 |
851 return true; 852 } | 449 ++fetchCycles; |
853 | 450 |
854 // If we've reached this point, we have not gotten any signals that 855 // cause fetch to change its status. Fetch remains the same as before. 856 return false; | 451 fetch(); 452 } else if (_status != IcacheMissStall) { 453 DPRINTF(Fetch, "Fetch: Running stage.\n"); 454 455 ++fetchCycles; 456 457 fetch(); 458 } |
857} 858 859template<class Impl> 860void | 459} 460 461template<class Impl> 462void |
861DefaultFetch<Impl>::fetch(bool &status_change) | 463SimpleFetch<Impl>::fetch() |
862{ 863 ////////////////////////////////////////// 864 // Start actual fetch 865 ////////////////////////////////////////// | 464{ 465 ////////////////////////////////////////// 466 // Start actual fetch 467 ////////////////////////////////////////// |
866 int tid = getFetchingThread(fetchPolicy); | |
867 | 468 |
868 if (tid == -1) { 869 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 870 871 // Breaks looping condition in tick() 872 threadFetched = numFetchingThreads; 873 return; 874 } 875 | |
876 // The current PC. | 469 // The current PC. |
877 Addr &fetch_PC = PC[tid]; | 470 Addr fetch_PC = cpu->readPC(); |
878 879 // Fault code for memory access. 880 Fault fault = NoFault; 881 882 // If returning from the delay of a cache miss, then update the status 883 // to running, otherwise do the cache access. Possibly move this up 884 // to tick() function. | 471 472 // Fault code for memory access. 473 Fault fault = NoFault; 474 475 // If returning from the delay of a cache miss, then update the status 476 // to running, otherwise do the cache access. Possibly move this up 477 // to tick() function. |
885 if (fetchStatus[tid] == IcacheMissComplete) { 886 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", 887 tid); | 478 if (_status == IcacheMissComplete) { 479 DPRINTF(Fetch, "Fetch: Icache miss is complete.\n"); |
888 | 480 |
889 fetchStatus[tid] = Running; 890 status_change = true; 891 } else if (fetchStatus[tid] == Running) { 892 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 893 "instruction, starting at PC %08p.\n", 894 tid, fetch_PC); | 481 // Reset the completion event to NULL. 482 memReq->completionEvent = NULL; |
895 | 483 |
896 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid); 897 if (!fetch_success) { 898 ++fetchMiscStallCycles; 899 return; 900 } | 484 _status = Running; |
901 } else { | 485 } else { |
902 if (fetchStatus[tid] == Idle) { 903 ++fetchIdleCycles; 904 } else if (fetchStatus[tid] == Blocked) { 905 ++fetchBlockedCycles; 906 } else if (fetchStatus[tid] == Squashing) { 907 ++fetchSquashCycles; 908 } else if (fetchStatus[tid] == IcacheMissStall) { 909 ++icacheStallCycles; 910 } | 486 DPRINTF(Fetch, "Fetch: Attempting to translate and read " 487 "instruction, starting at PC %08p.\n", 488 fetch_PC); |
911 | 489 |
912 // Status is Idle, Squashing, Blocked, or IcacheMissStall, so 913 // fetch should do nothing. 914 return; | 490 fault = fetchCacheLine(fetch_PC); |
915 } 916 | 491 } 492 |
917 ++fetchCycles; 918 919 // If we had a stall due to an icache miss, then return. 920 if (fetchStatus[tid] == IcacheMissStall) { 921 ++icacheStallCycles; 922 status_change = true; | 493 // If we had a stall due to an icache miss, then return. It'd 494 // be nicer if this were handled through the kind of fault that 495 // is returned by the function. 496 if (_status == IcacheMissStall) { |
923 return; 924 } 925 | 497 return; 498 } 499 |
500 // As far as timing goes, the CPU will need to send an event through 501 // the MemReq in order to be woken up once the memory access completes. 502 // Probably have a status on a per thread basis so each thread can 503 // block independently and be woken up independently. 504 |
|
926 Addr next_PC = fetch_PC; 927 InstSeqNum inst_seq; 928 MachInst inst; | 505 Addr next_PC = fetch_PC; 506 InstSeqNum inst_seq; 507 MachInst inst; |
929 ExtMachInst ext_inst; 930 // @todo: Fix this hack. 931 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; | 508 unsigned offset = fetch_PC & cacheBlkMask; 509 unsigned fetched; |
932 933 if (fault == NoFault) { 934 // If the read of the first instruction was successful, then grab the 935 // instructions from the rest of the cache line and put them into the 936 // queue heading to decode. 937 | 510 511 if (fault == NoFault) { 512 // If the read of the first instruction was successful, then grab the 513 // instructions from the rest of the cache line and put them into the 514 // queue heading to decode. 515 |
938 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 939 "decode.\n",tid); | 516 DPRINTF(Fetch, "Fetch: Adding instructions to queue to decode.\n"); |
940 | 517 |
518 ////////////////////////// 519 // Fetch first instruction 520 ////////////////////////// 521 |
|
941 // Need to keep track of whether or not a predicted branch 942 // ended this fetch block. 943 bool predicted_branch = false; 944 | 522 // Need to keep track of whether or not a predicted branch 523 // ended this fetch block. 524 bool predicted_branch = false; 525 |
945 for (; | 526 for (fetched = 0; |
946 offset < cacheBlkSize && | 527 offset < cacheBlkSize && |
947 numInst < fetchWidth && | 528 fetched < fetchWidth && |
948 !predicted_branch; | 529 !predicted_branch; |
949 ++numInst) { | 530 ++fetched) 531 { |
950 951 // Get a sequence number. 952 inst_seq = cpu->getAndIncrementInstSeq(); 953 954 // Make sure this is a valid index. 955 assert(offset <= cacheBlkSize - instSize); 956 957 // Get the instruction from the array of the cache line. 958 inst = gtoh(*reinterpret_cast<MachInst *> | 532 533 // Get a sequence number. 534 inst_seq = cpu->getAndIncrementInstSeq(); 535 536 // Make sure this is a valid index. 537 assert(offset <= cacheBlkSize - instSize); 538 539 // Get the instruction from the array of the cache line. 540 inst = gtoh(*reinterpret_cast<MachInst *> |
959 (&cacheData[tid][offset])); | 541 (&cacheData[offset])); |
960 | 542 |
961 ext_inst = TheISA::makeExtMI(inst, fetch_PC); 962 | |
963 // Create a new DynInst from the instruction fetched. | 543 // Create a new DynInst from the instruction fetched. |
964 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, 965 next_PC, | 544 DynInstPtr instruction = new DynInst(inst, fetch_PC, next_PC, |
966 inst_seq, cpu); | 545 inst_seq, cpu); |
967 instruction->setThread(tid); | |
968 | 546 |
969 instruction->setASID(tid); | 547 DPRINTF(Fetch, "Fetch: Instruction %i created, with PC %#x\n", 548 inst_seq, instruction->readPC()); |
970 | 549 |
971 instruction->setState(cpu->thread[tid]); | 550 DPRINTF(Fetch, "Fetch: Instruction opcode is: %03p\n", 551 OPCODE(inst)); |
972 | 552 |
973 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 974 "[sn:%lli]\n", 975 tid, instruction->readPC(), inst_seq); 976 977 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 978 tid, instruction->staticInst->disassemble(fetch_PC)); 979 | |
980 instruction->traceData = | 553 instruction->traceData = |
981 Trace::getInstRecord(curTick, cpu->xcBase(tid), cpu, | 554 Trace::getInstRecord(curTick, cpu->xcBase(), cpu, |
982 instruction->staticInst, | 555 instruction->staticInst, |
983 instruction->readPC(),tid); | 556 instruction->readPC(), 0); |
984 985 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC); 986 987 // Add instruction to the CPU's list of instructions. | 557 558 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC); 559 560 // Add instruction to the CPU's list of instructions. |
988 instruction->setInstListIt(cpu->addInst(instruction)); | 561 cpu->addInst(instruction); |
989 990 // Write the instruction to the first slot in the queue 991 // that heads to decode. | 562 563 // Write the instruction to the first slot in the queue 564 // that heads to decode. |
992 toDecode->insts[numInst] = instruction; | 565 toDecode->insts[fetched] = instruction; |
993 994 toDecode->size++; 995 996 // Increment stat of fetched instructions. 997 ++fetchedInsts; 998 999 // Move to the next instruction, unless we have a branch. 1000 fetch_PC = next_PC; 1001 | 566 567 toDecode->size++; 568 569 // Increment stat of fetched instructions. 570 ++fetchedInsts; 571 572 // Move to the next instruction, unless we have a branch. 573 fetch_PC = next_PC; 574 |
1002 if (instruction->isQuiesce()) { 1003 warn("%lli: Quiesce instruction encountered, halting fetch!", 1004 curTick); 1005 fetchStatus[tid] = QuiescePending; 1006 ++numInst; 1007 status_change = true; 1008 break; 1009 } 1010 | |
1011 offset+= instSize; 1012 } | 575 offset+= instSize; 576 } |
1013 } | |
1014 | 577 |
1015 if (numInst > 0) { 1016 wroteToTimeBuffer = true; | 578 fetch_nisn_dist.sample(fetched); |
1017 } 1018 1019 // Now that fetching is completed, update the PC to signify what the next | 579 } 580 581 // Now that fetching is completed, update the PC to signify what the next |
1020 // cycle will be. | 582 // cycle will be. Might want to move this to the beginning of this 583 // function so that the PC updates at the beginning of everything. 584 // Or might want to leave setting the PC to the main CPU, with fetch 585 // only changing the nextPC (will require correct determination of 586 // next PC). |
1021 if (fault == NoFault) { | 587 if (fault == NoFault) { |
1022 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC); 1023 1024 PC[tid] = next_PC; 1025 nextPC[tid] = next_PC + instSize; | 588 DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC); 589 cpu->setPC(next_PC); 590 cpu->setNextPC(next_PC + instSize); |
1026 } else { | 591 } else { |
1027 // We shouldn't be in an icache miss and also have a fault (an ITB 1028 // miss) 1029 if (fetchStatus[tid] == IcacheMissStall) { 1030 panic("Fetch should have exited prior to this!"); | 592 // If the issue was an icache miss, then we can just return and 593 // wait until it is handled. 594 if (_status == IcacheMissStall) { 595 return; |
1031 } 1032 | 596 } 597 |
1033 // Send the fault to commit. This thread will not do anything 1034 // until commit handles the fault. The only other way it can 1035 // wake up is if a squash comes along and changes the PC. 1036#if FULL_SYSTEM 1037 assert(numInst != fetchWidth); 1038 // Get a sequence number. 1039 inst_seq = cpu->getAndIncrementInstSeq(); 1040 // We will use a nop in order to carry the fault. 1041 ext_inst = TheISA::NoopMachInst; | 598 // Handle the fault. 599 // This stage will not be able to continue until all the ROB 600 // slots are empty, at which point the fault can be handled. 601 // The only other way it can wake up is if a squash comes along 602 // and changes the PC. Not sure how to handle that case...perhaps 603 // have it handled by the upper level CPU class which peeks into the 604 // time buffer and sees if a squash comes along, in which case it 605 // changes the status. |
1042 | 606 |
1043 // Create a new DynInst from the dummy nop. 1044 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, 1045 next_PC, 1046 inst_seq, cpu); 1047 instruction->setPredTarg(next_PC + instSize); 1048 instruction->setThread(tid); | 607 DPRINTF(Fetch, "Fetch: Blocked, need to handle the trap.\n"); |
1049 | 608 |
1050 instruction->setASID(tid); 1051 1052 instruction->setState(cpu->thread[tid]); 1053 1054 instruction->traceData = NULL; 1055 1056 instruction->setInstListIt(cpu->addInst(instruction)); 1057 1058 instruction->fault = fault; 1059 1060 toDecode->insts[numInst] = instruction; 1061 toDecode->size++; 1062 1063 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1064 1065 fetchStatus[tid] = TrapPending; 1066 status_change = true; 1067 1068 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); | 609 _status = Blocked; 610#if FULL_SYSTEM 611// cpu->trap(fault); 612 // Send a signal to the ROB indicating that there's a trap from the 613 // fetch stage that needs to be handled. Need to indicate that 614 // there's a fault, and the fault type. |
1069#else // !FULL_SYSTEM | 615#else // !FULL_SYSTEM |
1070 fatal("fault (%d) detected @ PC %08p", fault, PC[tid]); | 616 fatal("fault (%d) detected @ PC %08p", fault, cpu->readPC()); |
1071#endif // FULL_SYSTEM 1072 } 1073} | 617#endif // FULL_SYSTEM 618 } 619} |
1074 1075 1076/////////////////////////////////////// 1077// // 1078// SMT FETCH POLICY MAINTAINED HERE // 1079// // 1080/////////////////////////////////////// 1081template<class Impl> 1082int 1083DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1084{ 1085 if (numThreads > 1) { 1086 switch (fetch_priority) { 1087 1088 case SingleThread: 1089 return 0; 1090 1091 case RoundRobin: 1092 return roundRobin(); 1093 1094 case IQ: 1095 return iqCount(); 1096 1097 case LSQ: 1098 return lsqCount(); 1099 1100 case Branch: 1101 return branchCount(); 1102 1103 default: 1104 return -1; 1105 } 1106 } else { 1107 int tid = *((*activeThreads).begin()); 1108 1109 if (fetchStatus[tid] == Running || 1110 fetchStatus[tid] == IcacheMissComplete || 1111 fetchStatus[tid] == Idle) { 1112 return tid; 1113 } else { 1114 return -1; 1115 } 1116 } 1117 1118} 1119 1120 1121template<class Impl> 1122int 1123DefaultFetch<Impl>::roundRobin() 1124{ 1125 list<unsigned>::iterator pri_iter = priorityList.begin(); 1126 list<unsigned>::iterator end = priorityList.end(); 1127 1128 int high_pri; 1129 1130 while (pri_iter != end) { 1131 high_pri = *pri_iter; 1132 1133 assert(high_pri <= numThreads); 1134 1135 if (fetchStatus[high_pri] == Running || 1136 fetchStatus[high_pri] == IcacheMissComplete || 1137 fetchStatus[high_pri] == Idle) { 1138 1139 priorityList.erase(pri_iter); 1140 priorityList.push_back(high_pri); 1141 1142 return high_pri; 1143 } 1144 1145 pri_iter++; 1146 } 1147 1148 return -1; 1149} 1150 1151template<class Impl> 1152int 1153DefaultFetch<Impl>::iqCount() 1154{ 1155 priority_queue<unsigned> PQ; 1156 1157 list<unsigned>::iterator threads = (*activeThreads).begin(); 1158 1159 while (threads != (*activeThreads).end()) { 1160 unsigned tid = *threads++; 1161 1162 PQ.push(fromIEW->iewInfo[tid].iqCount); 1163 } 1164 1165 while (!PQ.empty()) { 1166 1167 unsigned high_pri = PQ.top(); 1168 1169 if (fetchStatus[high_pri] == Running || 1170 fetchStatus[high_pri] == IcacheMissComplete || 1171 fetchStatus[high_pri] == Idle) 1172 return high_pri; 1173 else 1174 PQ.pop(); 1175 1176 } 1177 1178 return -1; 1179} 1180 1181template<class Impl> 1182int 1183DefaultFetch<Impl>::lsqCount() 1184{ 1185 priority_queue<unsigned> PQ; 1186 1187 1188 list<unsigned>::iterator threads = (*activeThreads).begin(); 1189 1190 while (threads != (*activeThreads).end()) { 1191 unsigned tid = *threads++; 1192 1193 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1194 } 1195 1196 while (!PQ.empty()) { 1197 1198 unsigned high_pri = PQ.top(); 1199 1200 if (fetchStatus[high_pri] == Running || 1201 fetchStatus[high_pri] == IcacheMissComplete || 1202 fetchStatus[high_pri] == Idle) 1203 return high_pri; 1204 else 1205 PQ.pop(); 1206 1207 } 1208 1209 return -1; 1210} 1211 1212template<class Impl> 1213int 1214DefaultFetch<Impl>::branchCount() 1215{ 1216 list<unsigned>::iterator threads = (*activeThreads).begin(); 1217 1218 return *threads; 1219} | |