fetch_impl.hh (13981:577196ddd040) | fetch_impl.hh (14195:c5efdb3319aa) |
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1/* 2 * Copyright (c) 2010-2014 ARM Limited 3 * Copyright (c) 2012-2013 AMD 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 46 unchanged lines hidden (view full) --- 55#include "arch/isa_traits.hh" 56#include "arch/utility.hh" 57#include "arch/vtophys.hh" 58#include "base/random.hh" 59#include "base/types.hh" 60#include "config/the_isa.hh" 61#include "cpu/base.hh" 62//#include "cpu/checker/cpu.hh" | 1/* 2 * Copyright (c) 2010-2014 ARM Limited 3 * Copyright (c) 2012-2013 AMD 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 46 unchanged lines hidden (view full) --- 55#include "arch/isa_traits.hh" 56#include "arch/utility.hh" 57#include "arch/vtophys.hh" 58#include "base/random.hh" 59#include "base/types.hh" 60#include "config/the_isa.hh" 61#include "cpu/base.hh" 62//#include "cpu/checker/cpu.hh" |
63#include "cpu/o3/cpu.hh" |
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63#include "cpu/o3/fetch.hh" 64#include "cpu/exetrace.hh" 65#include "debug/Activity.hh" 66#include "debug/Drain.hh" 67#include "debug/Fetch.hh" | 64#include "cpu/o3/fetch.hh" 65#include "cpu/exetrace.hh" 66#include "debug/Activity.hh" 67#include "debug/Drain.hh" 68#include "debug/Fetch.hh" |
69#include "debug/O3CPU.hh" |
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68#include "debug/O3PipeView.hh" 69#include "mem/packet.hh" 70#include "params/DerivO3CPU.hh" 71#include "sim/byteswap.hh" 72#include "sim/core.hh" 73#include "sim/eventq.hh" 74#include "sim/full_system.hh" 75#include "sim/system.hh" --- 15 unchanged lines hidden (view full) --- 91 retryPkt(NULL), 92 retryTid(InvalidThreadID), 93 cacheBlkSize(cpu->cacheLineSize()), 94 fetchBufferSize(params->fetchBufferSize), 95 fetchBufferMask(fetchBufferSize - 1), 96 fetchQueueSize(params->fetchQueueSize), 97 numThreads(params->numThreads), 98 numFetchingThreads(params->smtNumFetchingThreads), | 70#include "debug/O3PipeView.hh" 71#include "mem/packet.hh" 72#include "params/DerivO3CPU.hh" 73#include "sim/byteswap.hh" 74#include "sim/core.hh" 75#include "sim/eventq.hh" 76#include "sim/full_system.hh" 77#include "sim/system.hh" --- 15 unchanged lines hidden (view full) --- 93 retryPkt(NULL), 94 retryTid(InvalidThreadID), 95 cacheBlkSize(cpu->cacheLineSize()), 96 fetchBufferSize(params->fetchBufferSize), 97 fetchBufferMask(fetchBufferSize - 1), 98 fetchQueueSize(params->fetchQueueSize), 99 numThreads(params->numThreads), 100 numFetchingThreads(params->smtNumFetchingThreads), |
101 icachePort(this, _cpu), |
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99 finishTranslationEvent(this) 100{ 101 if (numThreads > Impl::MaxThreads) 102 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 103 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 104 numThreads, static_cast<int>(Impl::MaxThreads)); 105 if (fetchWidth > Impl::MaxWidth) 106 fatal("fetchWidth (%d) is larger than compiled limit (%d),\n" --- 580 unchanged lines hidden (view full) --- 687 688 fetchBufferPC[tid] = fetchBufferBlockPC; 689 fetchBufferValid[tid] = false; 690 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 691 692 fetchedCacheLines++; 693 694 // Access the cache. | 102 finishTranslationEvent(this) 103{ 104 if (numThreads > Impl::MaxThreads) 105 fatal("numThreads (%d) is larger than compiled limit (%d),\n" 106 "\tincrease MaxThreads in src/cpu/o3/impl.hh\n", 107 numThreads, static_cast<int>(Impl::MaxThreads)); 108 if (fetchWidth > Impl::MaxWidth) 109 fatal("fetchWidth (%d) is larger than compiled limit (%d),\n" --- 580 unchanged lines hidden (view full) --- 690 691 fetchBufferPC[tid] = fetchBufferBlockPC; 692 fetchBufferValid[tid] = false; 693 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 694 695 fetchedCacheLines++; 696 697 // Access the cache. |
695 if (!cpu->getInstPort().sendTimingReq(data_pkt)) { | 698 if (!icachePort.sendTimingReq(data_pkt)) { |
696 assert(retryPkt == NULL); 697 assert(retryTid == InvalidThreadID); 698 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 699 700 fetchStatus[tid] = IcacheWaitRetry; 701 retryPkt = data_pkt; 702 retryTid = tid; 703 cacheBlocked = true; --- 713 unchanged lines hidden (view full) --- 1417void 1418DefaultFetch<Impl>::recvReqRetry() 1419{ 1420 if (retryPkt != NULL) { 1421 assert(cacheBlocked); 1422 assert(retryTid != InvalidThreadID); 1423 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1424 | 699 assert(retryPkt == NULL); 700 assert(retryTid == InvalidThreadID); 701 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 702 703 fetchStatus[tid] = IcacheWaitRetry; 704 retryPkt = data_pkt; 705 retryTid = tid; 706 cacheBlocked = true; --- 713 unchanged lines hidden (view full) --- 1420void 1421DefaultFetch<Impl>::recvReqRetry() 1422{ 1423 if (retryPkt != NULL) { 1424 assert(cacheBlocked); 1425 assert(retryTid != InvalidThreadID); 1426 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1427 |
1425 if (cpu->getInstPort().sendTimingReq(retryPkt)) { | 1428 if (icachePort.sendTimingReq(retryPkt)) { |
1426 fetchStatus[retryTid] = IcacheWaitResponse; 1427 // Notify Fetch Request probe when a retryPkt is successfully sent. 1428 // Note that notify must be called before retryPkt is set to NULL. 1429 ppFetchRequestSent->notify(retryPkt->req); 1430 retryPkt = NULL; 1431 retryTid = InvalidThreadID; 1432 cacheBlocked = false; 1433 } --- 231 unchanged lines hidden (view full) --- 1665 tid); 1666 } else { 1667 DPRINTF(Fetch, "[tid:%i] Unexpected fetch stall reason " 1668 "(Status: %i)\n", 1669 tid, fetchStatus[tid]); 1670 } 1671} 1672 | 1429 fetchStatus[retryTid] = IcacheWaitResponse; 1430 // Notify Fetch Request probe when a retryPkt is successfully sent. 1431 // Note that notify must be called before retryPkt is set to NULL. 1432 ppFetchRequestSent->notify(retryPkt->req); 1433 retryPkt = NULL; 1434 retryTid = InvalidThreadID; 1435 cacheBlocked = false; 1436 } --- 231 unchanged lines hidden (view full) --- 1668 tid); 1669 } else { 1670 DPRINTF(Fetch, "[tid:%i] Unexpected fetch stall reason " 1671 "(Status: %i)\n", 1672 tid, fetchStatus[tid]); 1673 } 1674} 1675 |
1676template<class Impl> 1677bool 1678DefaultFetch<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 1679{ 1680 DPRINTF(O3CPU, "Fetch unit received timing\n"); 1681 // We shouldn't ever get a cacheable block in Modified state 1682 assert(pkt->req->isUncacheable() || 1683 !(pkt->cacheResponding() && !pkt->hasSharers())); 1684 fetch->processCacheCompletion(pkt); 1685 1686 return true; 1687} 1688 1689template<class Impl> 1690void 1691DefaultFetch<Impl>::IcachePort::recvReqRetry() 1692{ 1693 fetch->recvReqRetry(); 1694} 1695 |
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1673#endif//__CPU_O3_FETCH_IMPL_HH__ | 1696#endif//__CPU_O3_FETCH_IMPL_HH__ |