fetch_impl.hh (12406:86bde4a026b5) fetch_impl.hh (12422:9d6162c8c1de)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * Copyright (c) 2012-2013 AMD
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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724 // until commit handles the fault. The only other way it can
725 // wake up is if a squash comes along and changes the PC.
726 TheISA::PCState fetchPC = pc[tid];
727
728 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
729 // We will use a nop in ordier to carry the fault.
730 DynInstPtr instruction = buildInst(tid, StaticInst::nopStaticInstPtr,
731 NULL, fetchPC, fetchPC, false);
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * Copyright (c) 2012-2013 AMD
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 715 unchanged lines hidden (view full) ---

724 // until commit handles the fault. The only other way it can
725 // wake up is if a squash comes along and changes the PC.
726 TheISA::PCState fetchPC = pc[tid];
727
728 DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
729 // We will use a nop in ordier to carry the fault.
730 DynInstPtr instruction = buildInst(tid, StaticInst::nopStaticInstPtr,
731 NULL, fetchPC, fetchPC, false);
732 instruction->setNotAnInst();
732
733 instruction->setPredTarg(fetchPC);
734 instruction->fault = fault;
735 wroteToTimeBuffer = true;
736
737 DPRINTF(Activity, "Activity this cycle.\n");
738 cpu->activityThisCycle();
739

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734 instruction->setPredTarg(fetchPC);
735 instruction->fault = fault;
736 wroteToTimeBuffer = true;
737
738 DPRINTF(Activity, "Activity this cycle.\n");
739 cpu->activityThisCycle();
740

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