fetch_impl.hh (10563:755b18321206) fetch_impl.hh (10566:c99c8d2a7c31)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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664 fetchStatus[tid] = NoGoodAddr;
665 delete mem_req;
666 memReq[tid] = NULL;
667 return;
668 }
669
670 // Build packet here.
671 PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 655 unchanged lines hidden (view full) ---

664 fetchStatus[tid] = NoGoodAddr;
665 delete mem_req;
666 memReq[tid] = NULL;
667 return;
668 }
669
670 // Build packet here.
671 PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
672 data_pkt->dataDynamicArray(new uint8_t[fetchBufferSize]);
672 data_pkt->dataDynamic(new uint8_t[fetchBufferSize]);
673
674 fetchBufferPC[tid] = fetchBufferBlockPC;
675 fetchBufferValid[tid] = false;
676 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
677
678 fetchedCacheLines++;
679
680 // Access the cache.

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674 fetchBufferPC[tid] = fetchBufferBlockPC;
675 fetchBufferValid[tid] = false;
676 DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
677
678 fetchedCacheLines++;
679
680 // Access the cache.

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