fetch_impl.hh (10244:d2deb51a4abf) fetch_impl.hh (10328:867b536a68be)
1/*
1/*
2 * Copyright (c) 2010-2013 ARM Limited
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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349 pc[tid] = cpu->pcState(tid);
350 fetchOffset[tid] = 0;
351 macroop[tid] = NULL;
352
353 delayedCommit[tid] = false;
354 memReq[tid] = NULL;
355
356 stalls[tid].decode = false;
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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349 pc[tid] = cpu->pcState(tid);
350 fetchOffset[tid] = 0;
351 macroop[tid] = NULL;
352
353 delayedCommit[tid] = false;
354 memReq[tid] = NULL;
355
356 stalls[tid].decode = false;
357 stalls[tid].rename = false;
358 stalls[tid].iew = false;
359 stalls[tid].commit = false;
360 stalls[tid].drain = false;
361
362 fetchBufferPC[tid] = 0;
363 fetchBufferValid[tid] = false;
364
365 priorityList.push_back(tid);
366 }
367

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430 assert(isDrained());
431 assert(retryPkt == NULL);
432 assert(retryTid == InvalidThreadID);
433 assert(!cacheBlocked);
434 assert(!interruptPending);
435
436 for (ThreadID i = 0; i < numThreads; ++i) {
437 assert(!memReq[i]);
357 stalls[tid].drain = false;
358
359 fetchBufferPC[tid] = 0;
360 fetchBufferValid[tid] = false;
361
362 priorityList.push_back(tid);
363 }
364

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427 assert(isDrained());
428 assert(retryPkt == NULL);
429 assert(retryTid == InvalidThreadID);
430 assert(!cacheBlocked);
431 assert(!interruptPending);
432
433 for (ThreadID i = 0; i < numThreads; ++i) {
434 assert(!memReq[i]);
438 assert(!stalls[i].decode);
439 assert(!stalls[i].rename);
440 assert(!stalls[i].iew);
441 assert(!stalls[i].commit);
442 assert(fetchStatus[i] == Idle || stalls[i].drain);
443 }
444
445 branchPred->drainSanityCheck();
446}
447
448template <class Impl>
449bool

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675 } else {
676 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
677 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
678 "response.\n", tid);
679 lastIcacheStall[tid] = curTick();
680 fetchStatus[tid] = IcacheWaitResponse;
681 }
682 } else {
435 assert(fetchStatus[i] == Idle || stalls[i].drain);
436 }
437
438 branchPred->drainSanityCheck();
439}
440
441template <class Impl>
442bool

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668 } else {
669 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
670 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
671 "response.\n", tid);
672 lastIcacheStall[tid] = curTick();
673 fetchStatus[tid] = IcacheWaitResponse;
674 }
675 } else {
683 if (!(numInst < fetchWidth)) {
676 // Don't send an instruction to decode if it can't handle it.
677 // Asynchronous nature of this function's calling means we have to
678 // check 2 signals to see if decode is stalled.
679 if (!(numInst < fetchWidth) || stalls[tid].decode ||
680 fromDecode->decodeBlock[tid]) {
684 assert(!finishTranslationEvent.scheduled());
685 finishTranslationEvent.setFault(fault);
686 finishTranslationEvent.setReq(mem_req);
687 cpu->schedule(finishTranslationEvent,
688 cpu->clockEdge(Cycles(1)));
689 return;
690 }
691 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",

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797 ret_val = true;
798 } else if (stalls[tid].drain) {
799 assert(cpu->isDraining());
800 DPRINTF(Fetch,"[tid:%i]: Drain stall detected.\n",tid);
801 ret_val = true;
802 } else if (stalls[tid].decode) {
803 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
804 ret_val = true;
681 assert(!finishTranslationEvent.scheduled());
682 finishTranslationEvent.setFault(fault);
683 finishTranslationEvent.setReq(mem_req);
684 cpu->schedule(finishTranslationEvent,
685 cpu->clockEdge(Cycles(1)));
686 return;
687 }
688 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",

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794 ret_val = true;
795 } else if (stalls[tid].drain) {
796 assert(cpu->isDraining());
797 DPRINTF(Fetch,"[tid:%i]: Drain stall detected.\n",tid);
798 ret_val = true;
799 } else if (stalls[tid].decode) {
800 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
801 ret_val = true;
805 } else if (stalls[tid].rename) {
806 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
807 ret_val = true;
808 } else if (stalls[tid].iew) {
809 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
810 ret_val = true;
811 } else if (stalls[tid].commit) {
812 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
813 ret_val = true;
814 }
815
816 return ret_val;
817}
818
819template<class Impl>
820typename DefaultFetch<Impl>::FetchStatus
821DefaultFetch<Impl>::updateFetchStatus()

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947 }
948
949 if (fromDecode->decodeUnblock[tid]) {
950 assert(stalls[tid].decode);
951 assert(!fromDecode->decodeBlock[tid]);
952 stalls[tid].decode = false;
953 }
954
802 }
803
804 return ret_val;
805}
806
807template<class Impl>
808typename DefaultFetch<Impl>::FetchStatus
809DefaultFetch<Impl>::updateFetchStatus()

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935 }
936
937 if (fromDecode->decodeUnblock[tid]) {
938 assert(stalls[tid].decode);
939 assert(!fromDecode->decodeBlock[tid]);
940 stalls[tid].decode = false;
941 }
942
955 if (fromRename->renameBlock[tid]) {
956 stalls[tid].rename = true;
957 }
958
959 if (fromRename->renameUnblock[tid]) {
960 assert(stalls[tid].rename);
961 assert(!fromRename->renameBlock[tid]);
962 stalls[tid].rename = false;
963 }
964
965 if (fromIEW->iewBlock[tid]) {
966 stalls[tid].iew = true;
967 }
968
969 if (fromIEW->iewUnblock[tid]) {
970 assert(stalls[tid].iew);
971 assert(!fromIEW->iewBlock[tid]);
972 stalls[tid].iew = false;
973 }
974
975 if (fromCommit->commitBlock[tid]) {
976 stalls[tid].commit = true;
977 }
978
979 if (fromCommit->commitUnblock[tid]) {
980 assert(stalls[tid].commit);
981 assert(!fromCommit->commitBlock[tid]);
982 stalls[tid].commit = false;
983 }
984
985 // Check squash signals from commit.
986 if (fromCommit->commitInfo[tid].squash) {
987
988 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
989 "from commit.\n",tid);
990 // In any case, squash.
991 squash(fromCommit->commitInfo[tid].pc,
992 fromCommit->commitInfo[tid].doneSeqNum,

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1008
1009 return true;
1010 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
1011 // Update the branch predictor if it wasn't a squashed instruction
1012 // that was broadcasted.
1013 branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid);
1014 }
1015
943 // Check squash signals from commit.
944 if (fromCommit->commitInfo[tid].squash) {
945
946 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
947 "from commit.\n",tid);
948 // In any case, squash.
949 squash(fromCommit->commitInfo[tid].pc,
950 fromCommit->commitInfo[tid].doneSeqNum,

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966
967 return true;
968 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
969 // Update the branch predictor if it wasn't a squashed instruction
970 // that was broadcasted.
971 branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid);
972 }
973
1016 // Check ROB squash signals from commit.
1017 if (fromCommit->commitInfo[tid].robSquashing) {
1018 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
1019
1020 // Continue to squash.
1021 fetchStatus[tid] = Squashing;
1022
1023 return true;
1024 }
1025
1026 // Check squash signals from decode.
1027 if (fromDecode->decodeInfo[tid].squash) {
1028 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
1029 "from decode.\n",tid);
1030
1031 // Update the branch predictor.
1032 if (fromDecode->decodeInfo[tid].branchMispredict) {
1033 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,

--- 626 unchanged lines hidden --- 		974 // Check squash signals from decode.
975 if (fromDecode->decodeInfo[tid].squash) {
976 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
977 "from decode.\n",tid);
978
979 // Update the branch predictor.
980 if (fromDecode->decodeInfo[tid].branchMispredict) {
981 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,

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