fetch_impl.hh (10020:2f33cb012383) fetch_impl.hh (10023:91faf6649de0)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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158std::string
159DefaultFetch<Impl>::name() const
160{
161 return cpu->name() + ".fetch";
162}
163
164template <class Impl>
165void
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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158std::string
159DefaultFetch<Impl>::name() const
160{
161 return cpu->name() + ".fetch";
162}
163
164template <class Impl>
165void
166DefaultFetch<Impl>::regProbePoints()
167{
168 ppFetch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Fetch");
169}
170
171template <class Impl>
172void
166DefaultFetch<Impl>::regStats()
167{
168 icacheStallCycles
169 .name(name() + ".icacheStallCycles")
170 .desc("Number of cycles fetch is stalled on an Icache miss")
171 .prereq(icacheStallCycles);
172
173 fetchedInsts

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396 // Only switch to IcacheAccessComplete if we're not stalled as well.
397 if (checkStall(tid)) {
398 fetchStatus[tid] = Blocked;
399 } else {
400 fetchStatus[tid] = IcacheAccessComplete;
401 }
402
403 pkt->req->setAccessLatency();
173DefaultFetch<Impl>::regStats()
174{
175 icacheStallCycles
176 .name(name() + ".icacheStallCycles")
177 .desc("Number of cycles fetch is stalled on an Icache miss")
178 .prereq(icacheStallCycles);
179
180 fetchedInsts

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403 // Only switch to IcacheAccessComplete if we're not stalled as well.
404 if (checkStall(tid)) {
405 fetchStatus[tid] = Blocked;
406 } else {
407 fetchStatus[tid] = IcacheAccessComplete;
408 }
409
410 pkt->req->setAccessLatency();
411 cpu->ppInstAccessComplete->notify(pkt);
404 // Reset the mem req to NULL.
405 delete pkt->req;
406 delete pkt;
407 memReq[tid] = NULL;
408}
409
410template <class Impl>
411void

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661 fetchStatus[tid] = IcacheWaitRetry;
662 retryPkt = data_pkt;
663 retryTid = tid;
664 cacheBlocked = true;
665 } else {
666 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
667 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
668 "response.\n", tid);
412 // Reset the mem req to NULL.
413 delete pkt->req;
414 delete pkt;
415 memReq[tid] = NULL;
416}
417
418template <class Impl>
419void

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669 fetchStatus[tid] = IcacheWaitRetry;
670 retryPkt = data_pkt;
671 retryTid = tid;
672 cacheBlocked = true;
673 } else {
674 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
675 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
676 "response.\n", tid);
669
670 lastIcacheStall[tid] = curTick();
671 fetchStatus[tid] = IcacheWaitResponse;
672 }
673 } else {
674 if (!(numInst < fetchWidth)) {
675 assert(!finishTranslationEvent.scheduled());
676 finishTranslationEvent.setFault(fault);
677 finishTranslationEvent.setReq(mem_req);

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1307 }
1308 newMacro |= staticInst->isLastMicroop();
1309 }
1310
1311 DynInstPtr instruction =
1312 buildInst(tid, staticInst, curMacroop,
1313 thisPC, nextPC, true);
1314
677 lastIcacheStall[tid] = curTick();
678 fetchStatus[tid] = IcacheWaitResponse;
679 }
680 } else {
681 if (!(numInst < fetchWidth)) {
682 assert(!finishTranslationEvent.scheduled());
683 finishTranslationEvent.setFault(fault);
684 finishTranslationEvent.setReq(mem_req);

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1314 }
1315 newMacro |= staticInst->isLastMicroop();
1316 }
1317
1318 DynInstPtr instruction =
1319 buildInst(tid, staticInst, curMacroop,
1320 thisPC, nextPC, true);
1321
1322 ppFetch->notify(instruction);
1315 numInst++;
1316
1317#if TRACING_ON
1318 if (DTRACE(O3PipeView)) {
1319 instruction->fetchTick = curTick();
1320 }
1321#endif
1322

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1324
1325#if TRACING_ON
1326 if (DTRACE(O3PipeView)) {
1327 instruction->fetchTick = curTick();
1328 }
1329#endif
1330

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