107 decodeToFetchDelay(params->decodeToFetchDelay), 108 renameToFetchDelay(params->renameToFetchDelay), 109 iewToFetchDelay(params->iewToFetchDelay), 110 commitToFetchDelay(params->commitToFetchDelay), 111 fetchWidth(params->fetchWidth), 112 cacheBlocked(false), 113 retryPkt(NULL), 114 retryTid(-1), 115 numThreads(params->numberOfThreads), 116 numFetchingThreads(params->smtNumFetchingThreads), 117 interruptPending(false), 118 drainPending(false), 119 switchedOut(false) 120{ 121 if (numThreads > Impl::MaxThreads) 122 fatal("numThreads is not a valid value\n"); 123 124 // Set fetch stage's status to inactive. 125 _status = Inactive; 126 127 std::string policy = params->smtFetchPolicy; 128 129 // Convert string to lowercase 130 std::transform(policy.begin(), policy.end(), policy.begin(), 131 (int(*)(int)) tolower); 132 133 // Figure out fetch policy 134 if (policy == "singlethread") { 135 fetchPolicy = SingleThread; 136 if (numThreads > 1) 137 panic("Invalid Fetch Policy for a SMT workload."); 138 } else if (policy == "roundrobin") { 139 fetchPolicy = RoundRobin; 140 DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 141 } else if (policy == "branch") { 142 fetchPolicy = Branch; 143 DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 144 } else if (policy == "iqcount") { 145 fetchPolicy = IQ; 146 DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 147 } else if (policy == "lsqcount") { 148 fetchPolicy = LSQ; 149 DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 150 } else { 151 fatal("Invalid Fetch Policy. Options Are: {SingleThread," 152 " RoundRobin,LSQcount,IQcount}\n"); 153 } 154 155 // Get the size of an instruction. 156 instSize = sizeof(TheISA::MachInst); 157} 158 159template <class Impl> 160std::string 161DefaultFetch<Impl>::name() const 162{ 163 return cpu->name() + ".fetch"; 164} 165 166template <class Impl> 167void 168DefaultFetch<Impl>::regStats() 169{ 170 icacheStallCycles 171 .name(name() + ".icacheStallCycles") 172 .desc("Number of cycles fetch is stalled on an Icache miss") 173 .prereq(icacheStallCycles); 174 175 fetchedInsts 176 .name(name() + ".Insts") 177 .desc("Number of instructions fetch has processed") 178 .prereq(fetchedInsts); 179 180 fetchedBranches 181 .name(name() + ".Branches") 182 .desc("Number of branches that fetch encountered") 183 .prereq(fetchedBranches); 184 185 predictedBranches 186 .name(name() + ".predictedBranches") 187 .desc("Number of branches that fetch has predicted taken") 188 .prereq(predictedBranches); 189 190 fetchCycles 191 .name(name() + ".Cycles") 192 .desc("Number of cycles fetch has run and was not squashing or" 193 " blocked") 194 .prereq(fetchCycles); 195 196 fetchSquashCycles 197 .name(name() + ".SquashCycles") 198 .desc("Number of cycles fetch has spent squashing") 199 .prereq(fetchSquashCycles); 200 201 fetchIdleCycles 202 .name(name() + ".IdleCycles") 203 .desc("Number of cycles fetch was idle") 204 .prereq(fetchIdleCycles); 205 206 fetchBlockedCycles 207 .name(name() + ".BlockedCycles") 208 .desc("Number of cycles fetch has spent blocked") 209 .prereq(fetchBlockedCycles); 210 211 fetchedCacheLines 212 .name(name() + ".CacheLines") 213 .desc("Number of cache lines fetched") 214 .prereq(fetchedCacheLines); 215 216 fetchMiscStallCycles 217 .name(name() + ".MiscStallCycles") 218 .desc("Number of cycles fetch has spent waiting on interrupts, or " 219 "bad addresses, or out of MSHRs") 220 .prereq(fetchMiscStallCycles); 221 222 fetchIcacheSquashes 223 .name(name() + ".IcacheSquashes") 224 .desc("Number of outstanding Icache misses that were squashed") 225 .prereq(fetchIcacheSquashes); 226 227 fetchNisnDist 228 .init(/* base value */ 0, 229 /* last value */ fetchWidth, 230 /* bucket size */ 1) 231 .name(name() + ".rateDist") 232 .desc("Number of instructions fetched each cycle (Total)") 233 .flags(Stats::pdf); 234 235 idleRate 236 .name(name() + ".idleRate") 237 .desc("Percent of cycles fetch was idle") 238 .prereq(idleRate); 239 idleRate = fetchIdleCycles * 100 / cpu->numCycles; 240 241 branchRate 242 .name(name() + ".branchRate") 243 .desc("Number of branch fetches per cycle") 244 .flags(Stats::total); 245 branchRate = fetchedBranches / cpu->numCycles; 246 247 fetchRate 248 .name(name() + ".rate") 249 .desc("Number of inst fetches per cycle") 250 .flags(Stats::total); 251 fetchRate = fetchedInsts / cpu->numCycles; 252 253 branchPred.regStats(); 254} 255 256template<class Impl> 257void 258DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr) 259{ 260 DPRINTF(Fetch, "Setting the CPU pointer.\n"); 261 cpu = cpu_ptr; 262 263 // Name is finally available, so create the port. 264 icachePort = new IcachePort(this); 265 266 icachePort->snoopRangeSent = false; 267 268#if USE_CHECKER 269 if (cpu->checker) { 270 cpu->checker->setIcachePort(icachePort); 271 } 272#endif 273 274 // Schedule fetch to get the correct PC from the CPU 275 // scheduleFetchStartupEvent(1); 276 277 // Fetch needs to start fetching instructions at the very beginning, 278 // so it must start up in active state. 279 switchToActive(); 280} 281 282template<class Impl> 283void 284DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 285{ 286 DPRINTF(Fetch, "Setting the time buffer pointer.\n"); 287 timeBuffer = time_buffer; 288 289 // Create wires to get information from proper places in time buffer. 290 fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 291 fromRename = timeBuffer->getWire(-renameToFetchDelay); 292 fromIEW = timeBuffer->getWire(-iewToFetchDelay); 293 fromCommit = timeBuffer->getWire(-commitToFetchDelay); 294} 295 296template<class Impl> 297void 298DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 299{ 300 DPRINTF(Fetch, "Setting active threads list pointer.\n"); 301 activeThreads = at_ptr; 302} 303 304template<class Impl> 305void 306DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 307{ 308 DPRINTF(Fetch, "Setting the fetch queue pointer.\n"); 309 fetchQueue = fq_ptr; 310 311 // Create wire to write information to proper place in fetch queue. 312 toDecode = fetchQueue->getWire(0); 313} 314 315template<class Impl> 316void 317DefaultFetch<Impl>::initStage() 318{ 319 // Setup PC and nextPC with initial state. 320 for (int tid = 0; tid < numThreads; tid++) { 321 PC[tid] = cpu->readPC(tid); 322 nextPC[tid] = cpu->readNextPC(tid); 323 nextNPC[tid] = cpu->readNextNPC(tid); 324 } 325 326 // Size of cache block. 327 cacheBlkSize = icachePort->peerBlockSize(); 328 329 // Create mask to get rid of offset bits. 330 cacheBlkMask = (cacheBlkSize - 1); 331 332 for (int tid=0; tid < numThreads; tid++) { 333 334 fetchStatus[tid] = Running; 335 336 priorityList.push_back(tid); 337 338 memReq[tid] = NULL; 339 340 // Create space to store a cache line. 341 cacheData[tid] = new uint8_t[cacheBlkSize]; 342 cacheDataPC[tid] = 0; 343 cacheDataValid[tid] = false; 344 345 stalls[tid].decode = false; 346 stalls[tid].rename = false; 347 stalls[tid].iew = false; 348 stalls[tid].commit = false; 349 } 350} 351 352template<class Impl> 353void 354DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 355{ 356 unsigned tid = pkt->req->getThreadNum(); 357 358 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 359 360 // Only change the status if it's still waiting on the icache access 361 // to return. 362 if (fetchStatus[tid] != IcacheWaitResponse || 363 pkt->req != memReq[tid] || 364 isSwitchedOut()) { 365 ++fetchIcacheSquashes; 366 delete pkt->req; 367 delete pkt; 368 return; 369 } 370 371 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize); 372 cacheDataValid[tid] = true; 373 374 if (!drainPending) { 375 // Wake up the CPU (if it went to sleep and was waiting on 376 // this completion event). 377 cpu->wakeCPU(); 378 379 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 380 tid); 381 382 switchToActive(); 383 } 384 385 // Only switch to IcacheAccessComplete if we're not stalled as well. 386 if (checkStall(tid)) { 387 fetchStatus[tid] = Blocked; 388 } else { 389 fetchStatus[tid] = IcacheAccessComplete; 390 } 391 392 // Reset the mem req to NULL. 393 delete pkt->req; 394 delete pkt; 395 memReq[tid] = NULL; 396} 397 398template <class Impl> 399bool 400DefaultFetch<Impl>::drain() 401{ 402 // Fetch is ready to drain at any time. 403 cpu->signalDrained(); 404 drainPending = true; 405 return true; 406} 407 408template <class Impl> 409void 410DefaultFetch<Impl>::resume() 411{ 412 drainPending = false; 413} 414 415template <class Impl> 416void 417DefaultFetch<Impl>::switchOut() 418{ 419 switchedOut = true; 420 // Branch predictor needs to have its state cleared. 421 branchPred.switchOut(); 422} 423 424template <class Impl> 425void 426DefaultFetch<Impl>::takeOverFrom() 427{ 428 // Reset all state 429 for (int i = 0; i < Impl::MaxThreads; ++i) { 430 stalls[i].decode = 0; 431 stalls[i].rename = 0; 432 stalls[i].iew = 0; 433 stalls[i].commit = 0; 434 PC[i] = cpu->readPC(i); 435 nextPC[i] = cpu->readNextPC(i); 436#if ISA_HAS_DELAY_SLOT 437 nextNPC[i] = cpu->readNextNPC(i); 438#else 439 nextNPC[i] = nextPC[i] + sizeof(TheISA::MachInst); 440#endif 441 fetchStatus[i] = Running; 442 } 443 numInst = 0; 444 wroteToTimeBuffer = false; 445 _status = Inactive; 446 switchedOut = false; 447 interruptPending = false; 448 branchPred.takeOverFrom(); 449} 450 451template <class Impl> 452void 453DefaultFetch<Impl>::wakeFromQuiesce() 454{ 455 DPRINTF(Fetch, "Waking up from quiesce\n"); 456 // Hopefully this is safe 457 // @todo: Allow other threads to wake from quiesce. 458 fetchStatus[0] = Running; 459} 460 461template <class Impl> 462inline void 463DefaultFetch<Impl>::switchToActive() 464{ 465 if (_status == Inactive) { 466 DPRINTF(Activity, "Activating stage.\n"); 467 468 cpu->activateStage(O3CPU::FetchIdx); 469 470 _status = Active; 471 } 472} 473 474template <class Impl> 475inline void 476DefaultFetch<Impl>::switchToInactive() 477{ 478 if (_status == Active) { 479 DPRINTF(Activity, "Deactivating stage.\n"); 480 481 cpu->deactivateStage(O3CPU::FetchIdx); 482 483 _status = Inactive; 484 } 485} 486 487template <class Impl> 488bool 489DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, 490 Addr &next_NPC) 491{ 492 // Do branch prediction check here. 493 // A bit of a misnomer...next_PC is actually the current PC until 494 // this function updates it. 495 bool predict_taken; 496 497 if (!inst->isControl()) { 498 next_PC = next_NPC; 499 next_NPC = next_NPC + instSize; 500 inst->setPredTarg(next_PC, next_NPC); 501 inst->setPredTaken(false); 502 return false; 503 } 504 505 int tid = inst->threadNumber; 506 Addr pred_PC = next_PC; 507 predict_taken = branchPred.predict(inst, pred_PC, tid); 508 509/* if (predict_taken) { 510 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n", 511 tid, pred_PC); 512 } else { 513 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); 514 }*/ 515 516#if ISA_HAS_DELAY_SLOT 517 next_PC = next_NPC; 518 if (predict_taken) 519 next_NPC = pred_PC; 520 else 521 next_NPC += instSize; 522#else 523 if (predict_taken) 524 next_PC = pred_PC; 525 else 526 next_PC += instSize; 527 next_NPC = next_PC + instSize; 528#endif 529/* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", 530 tid, next_PC, next_NPC);*/ 531 inst->setPredTarg(next_PC, next_NPC); 532 inst->setPredTaken(predict_taken); 533 534 ++fetchedBranches; 535 536 if (predict_taken) { 537 ++predictedBranches; 538 } 539 540 return predict_taken; 541} 542 543template <class Impl> 544bool 545DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid) 546{ 547 Fault fault = NoFault; 548 549 //AlphaDep 550 if (cacheBlocked) { 551 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 552 tid); 553 return false; 554 } else if (isSwitchedOut()) { 555 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 556 tid); 557 return false; 558 } else if (interruptPending && !(fetch_PC & 0x3)) { 559 // Hold off fetch from getting new instructions when: 560 // Cache is blocked, or 561 // while an interrupt is pending and we're not in PAL mode, or 562 // fetch is switched out. 563 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 564 tid); 565 return false; 566 } 567 568 // Align the fetch PC so it's at the start of a cache block. 569 Addr block_PC = icacheBlockAlignPC(fetch_PC); 570 571 // If we've already got the block, no need to try to fetch it again. 572 if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { 573 return true; 574 } 575 576 // Setup the memReq to do a read of the first instruction's address. 577 // Set the appropriate read size and flags as well. 578 // Build request here. 579 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, 580 fetch_PC, cpu->readCpuId(), tid); 581 582 memReq[tid] = mem_req; 583 584 // Translate the instruction request. 585 fault = cpu->translateInstReq(mem_req, cpu->thread[tid]); 586 587 // In the case of faults, the fetch stage may need to stall and wait 588 // for the ITB miss to be handled. 589 590 // If translation was successful, attempt to read the first 591 // instruction. 592 if (fault == NoFault) { 593#if 0 594 if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) || 595 memReq[tid]->isUncacheable()) { 596 DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a " 597 "misspeculating path)!", 598 memReq[tid]->paddr); 599 ret_fault = TheISA::genMachineCheckFault(); 600 return false; 601 } 602#endif 603 604 // Build packet here. 605 PacketPtr data_pkt = new Packet(mem_req, 606 MemCmd::ReadReq, Packet::Broadcast); 607 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 608 609 cacheDataPC[tid] = block_PC; 610 cacheDataValid[tid] = false; 611 612 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 613 614 fetchedCacheLines++; 615 616 // Now do the timing access to see whether or not the instruction 617 // exists within the cache. 618 if (!icachePort->sendTiming(data_pkt)) { 619 if (data_pkt->result == Packet::BadAddress) { 620 fault = TheISA::genMachineCheckFault(); 621 delete mem_req; 622 memReq[tid] = NULL; 623 } 624 assert(retryPkt == NULL); 625 assert(retryTid == -1); 626 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 627 fetchStatus[tid] = IcacheWaitRetry; 628 retryPkt = data_pkt; 629 retryTid = tid; 630 cacheBlocked = true; 631 return false; 632 } 633 634 DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid); 635 636 lastIcacheStall[tid] = curTick; 637 638 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 639 "response.\n", tid); 640 641 fetchStatus[tid] = IcacheWaitResponse; 642 } else { 643 delete mem_req; 644 memReq[tid] = NULL; 645 } 646 647 ret_fault = fault; 648 return true; 649} 650 651template <class Impl> 652inline void 653DefaultFetch<Impl>::doSquash(const Addr &new_PC, 654 const Addr &new_NPC, unsigned tid) 655{ 656 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n", 657 tid, new_PC, new_NPC); 658 659 PC[tid] = new_PC; 660 nextPC[tid] = new_NPC; 661 nextNPC[tid] = new_NPC + instSize; 662 663 // Clear the icache miss if it's outstanding. 664 if (fetchStatus[tid] == IcacheWaitResponse) { 665 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 666 tid); 667 memReq[tid] = NULL; 668 } 669 670 // Get rid of the retrying packet if it was from this thread. 671 if (retryTid == tid) { 672 assert(cacheBlocked); 673 cacheBlocked = false; 674 retryTid = -1; 675 delete retryPkt->req; 676 delete retryPkt; 677 retryPkt = NULL; 678 } 679 680 fetchStatus[tid] = Squashing; 681 682 ++fetchSquashCycles; 683} 684 685template<class Impl> 686void 687DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC, 688 const InstSeqNum &seq_num, 689 unsigned tid) 690{ 691 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 692 693 doSquash(new_PC, new_NPC, tid); 694 695 // Tell the CPU to remove any instructions that are in flight between 696 // fetch and decode. 697 cpu->removeInstsUntil(seq_num, tid); 698} 699 700template<class Impl> 701bool 702DefaultFetch<Impl>::checkStall(unsigned tid) const 703{ 704 bool ret_val = false; 705 706 if (cpu->contextSwitch) { 707 DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 708 ret_val = true; 709 } else if (stalls[tid].decode) { 710 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 711 ret_val = true; 712 } else if (stalls[tid].rename) { 713 DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 714 ret_val = true; 715 } else if (stalls[tid].iew) { 716 DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 717 ret_val = true; 718 } else if (stalls[tid].commit) { 719 DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 720 ret_val = true; 721 } 722 723 return ret_val; 724} 725 726template<class Impl> 727typename DefaultFetch<Impl>::FetchStatus 728DefaultFetch<Impl>::updateFetchStatus() 729{ 730 //Check Running 731 std::list<unsigned>::iterator threads = activeThreads->begin(); 732 std::list<unsigned>::iterator end = activeThreads->end(); 733 734 while (threads != end) { 735 unsigned tid = *threads++; 736 737 if (fetchStatus[tid] == Running || 738 fetchStatus[tid] == Squashing || 739 fetchStatus[tid] == IcacheAccessComplete) { 740 741 if (_status == Inactive) { 742 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 743 744 if (fetchStatus[tid] == IcacheAccessComplete) { 745 DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 746 "completion\n",tid); 747 } 748 749 cpu->activateStage(O3CPU::FetchIdx); 750 } 751 752 return Active; 753 } 754 } 755 756 // Stage is switching from active to inactive, notify CPU of it. 757 if (_status == Active) { 758 DPRINTF(Activity, "Deactivating stage.\n"); 759 760 cpu->deactivateStage(O3CPU::FetchIdx); 761 } 762 763 return Inactive; 764} 765 766template <class Impl> 767void 768DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC, 769 const InstSeqNum &seq_num, 770 bool squash_delay_slot, unsigned tid) 771{ 772 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 773 774 doSquash(new_PC, new_NPC, tid); 775 776#if ISA_HAS_DELAY_SLOT 777 // Tell the CPU to remove any instructions that are not in the ROB. 778 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num); 779#else 780 // Tell the CPU to remove any instructions that are not in the ROB. 781 cpu->removeInstsNotInROB(tid, true, 0); 782#endif 783} 784 785template <class Impl> 786void 787DefaultFetch<Impl>::tick() 788{ 789 std::list<unsigned>::iterator threads = activeThreads->begin(); 790 std::list<unsigned>::iterator end = activeThreads->end(); 791 bool status_change = false; 792 793 wroteToTimeBuffer = false; 794 795 while (threads != end) { 796 unsigned tid = *threads++; 797 798 // Check the signals for each thread to determine the proper status 799 // for each thread. 800 bool updated_status = checkSignalsAndUpdate(tid); 801 status_change = status_change || updated_status; 802 } 803 804 DPRINTF(Fetch, "Running stage.\n"); 805 806 // Reset the number of the instruction we're fetching. 807 numInst = 0; 808 809#if FULL_SYSTEM 810 if (fromCommit->commitInfo[0].interruptPending) { 811 interruptPending = true; 812 } 813 814 if (fromCommit->commitInfo[0].clearInterrupt) { 815 interruptPending = false; 816 } 817#endif 818 819 for (threadFetched = 0; threadFetched < numFetchingThreads; 820 threadFetched++) { 821 // Fetch each of the actively fetching threads. 822 fetch(status_change); 823 } 824 825 // Record number of instructions fetched this cycle for distribution. 826 fetchNisnDist.sample(numInst); 827 828 if (status_change) { 829 // Change the fetch stage status if there was a status change. 830 _status = updateFetchStatus(); 831 } 832 833 // If there was activity this cycle, inform the CPU of it. 834 if (wroteToTimeBuffer || cpu->contextSwitch) { 835 DPRINTF(Activity, "Activity this cycle.\n"); 836 837 cpu->activityThisCycle(); 838 } 839} 840 841template <class Impl> 842bool 843DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) 844{ 845 // Update the per thread stall statuses. 846 if (fromDecode->decodeBlock[tid]) { 847 stalls[tid].decode = true; 848 } 849 850 if (fromDecode->decodeUnblock[tid]) { 851 assert(stalls[tid].decode); 852 assert(!fromDecode->decodeBlock[tid]); 853 stalls[tid].decode = false; 854 } 855 856 if (fromRename->renameBlock[tid]) { 857 stalls[tid].rename = true; 858 } 859 860 if (fromRename->renameUnblock[tid]) { 861 assert(stalls[tid].rename); 862 assert(!fromRename->renameBlock[tid]); 863 stalls[tid].rename = false; 864 } 865 866 if (fromIEW->iewBlock[tid]) { 867 stalls[tid].iew = true; 868 } 869 870 if (fromIEW->iewUnblock[tid]) { 871 assert(stalls[tid].iew); 872 assert(!fromIEW->iewBlock[tid]); 873 stalls[tid].iew = false; 874 } 875 876 if (fromCommit->commitBlock[tid]) { 877 stalls[tid].commit = true; 878 } 879 880 if (fromCommit->commitUnblock[tid]) { 881 assert(stalls[tid].commit); 882 assert(!fromCommit->commitBlock[tid]); 883 stalls[tid].commit = false; 884 } 885 886 // Check squash signals from commit. 887 if (fromCommit->commitInfo[tid].squash) { 888 889 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 890 "from commit.\n",tid); 891 892#if ISA_HAS_DELAY_SLOT 893 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 894#else 895 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum; 896#endif 897 // In any case, squash. 898 squash(fromCommit->commitInfo[tid].nextPC, 899 fromCommit->commitInfo[tid].nextNPC, 900 doneSeqNum, 901 fromCommit->commitInfo[tid].squashDelaySlot, 902 tid); 903 904 // Also check if there's a mispredict that happened. 905 if (fromCommit->commitInfo[tid].branchMispredict) { 906 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 907 fromCommit->commitInfo[tid].nextPC, 908 fromCommit->commitInfo[tid].branchTaken, 909 tid); 910 } else { 911 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 912 tid); 913 } 914 915 return true; 916 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 917 // Update the branch predictor if it wasn't a squashed instruction 918 // that was broadcasted. 919 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 920 } 921 922 // Check ROB squash signals from commit. 923 if (fromCommit->commitInfo[tid].robSquashing) { 924 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 925 926 // Continue to squash. 927 fetchStatus[tid] = Squashing; 928 929 return true; 930 } 931 932 // Check squash signals from decode. 933 if (fromDecode->decodeInfo[tid].squash) { 934 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 935 "from decode.\n",tid); 936 937 // Update the branch predictor. 938 if (fromDecode->decodeInfo[tid].branchMispredict) { 939 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 940 fromDecode->decodeInfo[tid].nextPC, 941 fromDecode->decodeInfo[tid].branchTaken, 942 tid); 943 } else { 944 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 945 tid); 946 } 947 948 if (fetchStatus[tid] != Squashing) { 949 950#if ISA_HAS_DELAY_SLOT 951 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum; 952#else 953 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum; 954#endif 955 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n", 956 fromDecode->decodeInfo[tid].nextPC, 957 fromDecode->decodeInfo[tid].nextNPC); 958 // Squash unless we're already squashing 959 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 960 fromDecode->decodeInfo[tid].nextNPC, 961 doneSeqNum, 962 tid); 963 964 return true; 965 } 966 } 967 968 if (checkStall(tid) && 969 fetchStatus[tid] != IcacheWaitResponse && 970 fetchStatus[tid] != IcacheWaitRetry) { 971 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 972 973 fetchStatus[tid] = Blocked; 974 975 return true; 976 } 977 978 if (fetchStatus[tid] == Blocked || 979 fetchStatus[tid] == Squashing) { 980 // Switch status to running if fetch isn't being told to block or 981 // squash this cycle. 982 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 983 tid); 984 985 fetchStatus[tid] = Running; 986 987 return true; 988 } 989 990 // If we've reached this point, we have not gotten any signals that 991 // cause fetch to change its status. Fetch remains the same as before. 992 return false; 993} 994 995template<class Impl> 996void 997DefaultFetch<Impl>::fetch(bool &status_change) 998{ 999 ////////////////////////////////////////// 1000 // Start actual fetch 1001 ////////////////////////////////////////// 1002 int tid = getFetchingThread(fetchPolicy); 1003 1004 if (tid == -1 || drainPending) { 1005 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1006 1007 // Breaks looping condition in tick() 1008 threadFetched = numFetchingThreads; 1009 return; 1010 } 1011 1012 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1013 1014 // The current PC. 1015 Addr &fetch_PC = PC[tid]; 1016 1017 Addr &fetch_NPC = nextPC[tid]; 1018 1019 // Fault code for memory access. 1020 Fault fault = NoFault; 1021 1022 // If returning from the delay of a cache miss, then update the status 1023 // to running, otherwise do the cache access. Possibly move this up 1024 // to tick() function. 1025 if (fetchStatus[tid] == IcacheAccessComplete) { 1026 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", 1027 tid); 1028 1029 fetchStatus[tid] = Running; 1030 status_change = true; 1031 } else if (fetchStatus[tid] == Running) { 1032 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1033 "instruction, starting at PC %08p.\n", 1034 tid, fetch_PC); 1035 1036 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid); 1037 if (!fetch_success) { 1038 if (cacheBlocked) { 1039 ++icacheStallCycles; 1040 } else { 1041 ++fetchMiscStallCycles; 1042 } 1043 return; 1044 } 1045 } else { 1046 if (fetchStatus[tid] == Idle) { 1047 ++fetchIdleCycles; 1048 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1049 } else if (fetchStatus[tid] == Blocked) { 1050 ++fetchBlockedCycles; 1051 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1052 } else if (fetchStatus[tid] == Squashing) { 1053 ++fetchSquashCycles; 1054 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1055 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1056 ++icacheStallCycles; 1057 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid); 1058 } 1059 1060 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so 1061 // fetch should do nothing. 1062 return; 1063 } 1064 1065 ++fetchCycles; 1066 1067 // If we had a stall due to an icache miss, then return. 1068 if (fetchStatus[tid] == IcacheWaitResponse) { 1069 ++icacheStallCycles; 1070 status_change = true; 1071 return; 1072 } 1073 1074 Addr next_PC = fetch_PC; 1075 Addr next_NPC = fetch_NPC; 1076 1077 InstSeqNum inst_seq; 1078 MachInst inst; 1079 ExtMachInst ext_inst; 1080 // @todo: Fix this hack. 1081 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; 1082 1083 if (fault == NoFault) { 1084 // If the read of the first instruction was successful, then grab the 1085 // instructions from the rest of the cache line and put them into the 1086 // queue heading to decode. 1087 1088 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1089 "decode.\n",tid); 1090 1091 // Need to keep track of whether or not a predicted branch 1092 // ended this fetch block. 1093 bool predicted_branch = false; 1094 1095 for (; 1096 offset < cacheBlkSize && 1097 numInst < fetchWidth && 1098 !predicted_branch; 1099 ++numInst) { 1100 1101 // If we're branching after this instruction, quite fetching 1102 // from the same block then. 1103 predicted_branch = 1104 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC); 1105 if (predicted_branch) { 1106 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n", 1107 fetch_PC, fetch_NPC); 1108 } 1109 1110 1111 // Get a sequence number. 1112 inst_seq = cpu->getAndIncrementInstSeq(); 1113 1114 // Make sure this is a valid index. 1115 assert(offset <= cacheBlkSize - instSize); 1116 1117 // Get the instruction from the array of the cache line. 1118 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1119 (&cacheData[tid][offset])); 1120
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1126 // Create a new DynInst from the instruction fetched. 1127 DynInstPtr instruction = new DynInst(ext_inst, 1128 fetch_PC, fetch_NPC, 1129 next_PC, next_NPC, 1130 inst_seq, cpu); 1131 instruction->setTid(tid); 1132 1133 instruction->setASID(tid); 1134 1135 instruction->setThreadState(cpu->thread[tid]); 1136 1137 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1138 "[sn:%lli]\n", 1139 tid, instruction->readPC(), inst_seq); 1140 1141 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); 1142 1143 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1144 tid, instruction->staticInst->disassemble(fetch_PC)); 1145 1146 instruction->traceData = 1147 Trace::getInstRecord(curTick, cpu->tcBase(tid), 1148 instruction->staticInst, 1149 instruction->readPC()); 1150 1151 ///FIXME This needs to be more robust in dealing with delay slots 1152#if !ISA_HAS_DELAY_SLOT 1153 predicted_branch |= 1154#endif 1155 lookupAndUpdateNextPC(instruction, next_PC, next_NPC); 1156 predicted_branch |= (next_PC != fetch_NPC); 1157 1158 // Add instruction to the CPU's list of instructions. 1159 instruction->setInstListIt(cpu->addInst(instruction)); 1160 1161 // Write the instruction to the first slot in the queue 1162 // that heads to decode. 1163 toDecode->insts[numInst] = instruction; 1164 1165 toDecode->size++; 1166 1167 // Increment stat of fetched instructions. 1168 ++fetchedInsts; 1169 1170 // Move to the next instruction, unless we have a branch. 1171 fetch_PC = next_PC; 1172 fetch_NPC = next_NPC; 1173 1174 if (instruction->isQuiesce()) { 1175 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1176 curTick); 1177 fetchStatus[tid] = QuiescePending; 1178 ++numInst; 1179 status_change = true; 1180 break; 1181 } 1182 1183 offset += instSize; 1184 } 1185 1186 if (offset >= cacheBlkSize) { 1187 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1188 "block.\n", tid); 1189 } else if (numInst >= fetchWidth) { 1190 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1191 "for this cycle.\n", tid); 1192 } else if (predicted_branch) { 1193 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1194 "instruction encountered.\n", tid); 1195 } 1196 } 1197 1198 if (numInst > 0) { 1199 wroteToTimeBuffer = true; 1200 } 1201 1202 // Now that fetching is completed, update the PC to signify what the next 1203 // cycle will be. 1204 if (fault == NoFault) { 1205 PC[tid] = next_PC; 1206 nextPC[tid] = next_NPC; 1207 nextNPC[tid] = next_NPC + instSize; 1208#if ISA_HAS_DELAY_SLOT 1209 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]); 1210#else 1211 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC); 1212#endif 1213 } else { 1214 // We shouldn't be in an icache miss and also have a fault (an ITB 1215 // miss) 1216 if (fetchStatus[tid] == IcacheWaitResponse) { 1217 panic("Fetch should have exited prior to this!"); 1218 } 1219 1220 // Send the fault to commit. This thread will not do anything 1221 // until commit handles the fault. The only other way it can 1222 // wake up is if a squash comes along and changes the PC. 1223#if FULL_SYSTEM 1224 assert(numInst != fetchWidth); 1225 // Get a sequence number. 1226 inst_seq = cpu->getAndIncrementInstSeq(); 1227 // We will use a nop in order to carry the fault. 1228 ext_inst = TheISA::NoopMachInst; 1229 1230 // Create a new DynInst from the dummy nop. 1231 DynInstPtr instruction = new DynInst(ext_inst, 1232 fetch_PC, fetch_NPC, 1233 next_PC, next_NPC, 1234 inst_seq, cpu); 1235 instruction->setPredTarg(next_PC, next_NPC); 1236 instruction->setTid(tid); 1237 1238 instruction->setASID(tid); 1239 1240 instruction->setThreadState(cpu->thread[tid]); 1241 1242 instruction->traceData = NULL; 1243 1244 instruction->setInstListIt(cpu->addInst(instruction)); 1245 1246 instruction->fault = fault; 1247 1248 toDecode->insts[numInst] = instruction; 1249 toDecode->size++; 1250 1251 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1252 1253 fetchStatus[tid] = TrapPending; 1254 status_change = true; 1255#else // !FULL_SYSTEM 1256 fetchStatus[tid] = TrapPending; 1257 status_change = true; 1258 1259#endif // FULL_SYSTEM 1260 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", 1261 tid, fault->name(), PC[tid]); 1262 } 1263} 1264 1265template<class Impl> 1266void 1267DefaultFetch<Impl>::recvRetry() 1268{ 1269 if (retryPkt != NULL) { 1270 assert(cacheBlocked); 1271 assert(retryTid != -1); 1272 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1273 1274 if (icachePort->sendTiming(retryPkt)) { 1275 fetchStatus[retryTid] = IcacheWaitResponse; 1276 retryPkt = NULL; 1277 retryTid = -1; 1278 cacheBlocked = false; 1279 } 1280 } else { 1281 assert(retryTid == -1); 1282 // Access has been squashed since it was sent out. Just clear 1283 // the cache being blocked. 1284 cacheBlocked = false; 1285 } 1286} 1287 1288/////////////////////////////////////// 1289// // 1290// SMT FETCH POLICY MAINTAINED HERE // 1291// // 1292/////////////////////////////////////// 1293template<class Impl> 1294int 1295DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1296{ 1297 if (numThreads > 1) { 1298 switch (fetch_priority) { 1299 1300 case SingleThread: 1301 return 0; 1302 1303 case RoundRobin: 1304 return roundRobin(); 1305 1306 case IQ: 1307 return iqCount(); 1308 1309 case LSQ: 1310 return lsqCount(); 1311 1312 case Branch: 1313 return branchCount(); 1314 1315 default: 1316 return -1; 1317 } 1318 } else { 1319 std::list<unsigned>::iterator thread = activeThreads->begin(); 1320 assert(thread != activeThreads->end()); 1321 int tid = *thread; 1322 1323 if (fetchStatus[tid] == Running || 1324 fetchStatus[tid] == IcacheAccessComplete || 1325 fetchStatus[tid] == Idle) { 1326 return tid; 1327 } else { 1328 return -1; 1329 } 1330 } 1331 1332} 1333 1334 1335template<class Impl> 1336int 1337DefaultFetch<Impl>::roundRobin() 1338{ 1339 std::list<unsigned>::iterator pri_iter = priorityList.begin(); 1340 std::list<unsigned>::iterator end = priorityList.end(); 1341 1342 int high_pri; 1343 1344 while (pri_iter != end) { 1345 high_pri = *pri_iter; 1346 1347 assert(high_pri <= numThreads); 1348 1349 if (fetchStatus[high_pri] == Running || 1350 fetchStatus[high_pri] == IcacheAccessComplete || 1351 fetchStatus[high_pri] == Idle) { 1352 1353 priorityList.erase(pri_iter); 1354 priorityList.push_back(high_pri); 1355 1356 return high_pri; 1357 } 1358 1359 pri_iter++; 1360 } 1361 1362 return -1; 1363} 1364 1365template<class Impl> 1366int 1367DefaultFetch<Impl>::iqCount() 1368{ 1369 std::priority_queue<unsigned> PQ; 1370 1371 std::list<unsigned>::iterator threads = activeThreads->begin(); 1372 std::list<unsigned>::iterator end = activeThreads->end(); 1373 1374 while (threads != end) { 1375 unsigned tid = *threads++; 1376 1377 PQ.push(fromIEW->iewInfo[tid].iqCount); 1378 } 1379 1380 while (!PQ.empty()) { 1381 1382 unsigned high_pri = PQ.top(); 1383 1384 if (fetchStatus[high_pri] == Running || 1385 fetchStatus[high_pri] == IcacheAccessComplete || 1386 fetchStatus[high_pri] == Idle) 1387 return high_pri; 1388 else 1389 PQ.pop(); 1390 1391 } 1392 1393 return -1; 1394} 1395 1396template<class Impl> 1397int 1398DefaultFetch<Impl>::lsqCount() 1399{ 1400 std::priority_queue<unsigned> PQ; 1401 1402 std::list<unsigned>::iterator threads = activeThreads->begin(); 1403 std::list<unsigned>::iterator end = activeThreads->end(); 1404 1405 while (threads != end) { 1406 unsigned tid = *threads++; 1407 1408 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1409 } 1410 1411 while (!PQ.empty()) { 1412 1413 unsigned high_pri = PQ.top(); 1414 1415 if (fetchStatus[high_pri] == Running || 1416 fetchStatus[high_pri] == IcacheAccessComplete || 1417 fetchStatus[high_pri] == Idle) 1418 return high_pri; 1419 else 1420 PQ.pop(); 1421 1422 } 1423 1424 return -1; 1425} 1426 1427template<class Impl> 1428int 1429DefaultFetch<Impl>::branchCount() 1430{ 1431 std::list<unsigned>::iterator thread = activeThreads->begin(); 1432 assert(thread != activeThreads->end()); 1433 unsigned tid = *thread; 1434 1435 panic("Branch Count Fetch policy unimplemented\n"); 1436 return 0 * tid; 1437}
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