1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 607 unchanged lines hidden (view full) --- 616 617 cacheDataPC[tid] = block_PC; 618 cacheDataValid[tid] = false; 619 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 620 621 fetchedCacheLines++; 622 623 // Access the cache. |
624 if (!cpu->getInstPort().sendTimingReq(data_pkt)) { |
625 assert(retryPkt == NULL); 626 assert(retryTid == InvalidThreadID); 627 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 628 629 fetchStatus[tid] = IcacheWaitRetry; 630 retryPkt = data_pkt; 631 retryTid = tid; 632 cacheBlocked = true; --- 718 unchanged lines hidden (view full) --- 1351void 1352DefaultFetch<Impl>::recvRetry() 1353{ 1354 if (retryPkt != NULL) { 1355 assert(cacheBlocked); 1356 assert(retryTid != InvalidThreadID); 1357 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1358 |
1359 if (cpu->getInstPort().sendTimingReq(retryPkt)) { |
1360 fetchStatus[retryTid] = IcacheWaitResponse; 1361 retryPkt = NULL; 1362 retryTid = InvalidThreadID; 1363 cacheBlocked = false; 1364 } 1365 } else { 1366 assert(retryTid == InvalidThreadID); 1367 // Access has been squashed since it was sent out. Just clear --- 240 unchanged lines hidden --- |