1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 302 unchanged lines hidden (view full) --- 311} 312 313template<class Impl> 314void 315DefaultFetch<Impl>::initStage() 316{ 317 // Setup PC and nextPC with initial state. 318 for (ThreadID tid = 0; tid < numThreads; tid++) { |
319 pc[tid] = cpu->pcState(tid); |
320 } 321 322 for (ThreadID tid = 0; tid < numThreads; tid++) { 323 324 fetchStatus[tid] = Running; 325 326 priorityList.push_back(tid); 327 --- 110 unchanged lines hidden (view full) --- 438DefaultFetch<Impl>::takeOverFrom() 439{ 440 // Reset all state 441 for (ThreadID i = 0; i < Impl::MaxThreads; ++i) { 442 stalls[i].decode = 0; 443 stalls[i].rename = 0; 444 stalls[i].iew = 0; 445 stalls[i].commit = 0; |
446 pc[i] = cpu->pcState(i); |
447 fetchStatus[i] = Running; 448 } 449 numInst = 0; 450 wroteToTimeBuffer = false; 451 _status = Inactive; 452 switchedOut = false; 453 interruptPending = false; 454 branchPred.takeOverFrom(); --- 32 unchanged lines hidden (view full) --- 487 cpu->deactivateStage(O3CPU::FetchIdx); 488 489 _status = Inactive; 490 } 491} 492 493template <class Impl> 494bool |
495DefaultFetch 496 DynInstPtr &inst, TheISA::PCState &nextPC) |
497{ 498 // Do branch prediction check here. 499 // A bit of a misnomer...next_PC is actually the current PC until 500 // this function updates it. 501 bool predict_taken; 502 503 if (!inst->isControl()) { |
504 TheISA::advancePC(nextPC, inst->staticInst); 505 inst->setPredTarg(nextPC); |
506 inst->setPredTaken(false); 507 return false; 508 } 509 |
510 ThreadID tid = inst->threadNumber; |
511 predict_taken = branchPred.predict(inst, nextPC, tid); |
512 513 if (predict_taken) { |
514 DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n", 515 tid, inst->seqNum, nextPC); |
516 } else { 517 DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", 518 tid, inst->seqNum); 519 } 520 |
521 DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n", 522 tid, inst->seqNum, nextPC); 523 inst->setPredTarg(nextPC); |
524 inst->setPredTaken(predict_taken); 525 526 ++fetchedBranches; 527 528 if (predict_taken) { 529 ++predictedBranches; 530 } 531 --- 102 unchanged lines hidden (view full) --- 634 } 635 636 ret_fault = fault; 637 return true; 638} 639 640template <class Impl> 641inline void |
642DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid) |
643{ |
644 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n", 645 tid, newPC); |
646 |
647 pc[tid] = newPC; |
648 649 // Clear the icache miss if it's outstanding. 650 if (fetchStatus[tid] == IcacheWaitResponse) { 651 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 652 tid); 653 memReq[tid] = NULL; 654 } 655 --- 10 unchanged lines hidden (view full) --- 666 667 fetchStatus[tid] = Squashing; 668 669 ++fetchSquashCycles; 670} 671 672template<class Impl> 673void |
674DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC, |
675 const InstSeqNum &seq_num, ThreadID tid) 676{ |
677 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid); |
678 |
679 doSquash(newPC, tid); |
680 681 // Tell the CPU to remove any instructions that are in flight between 682 // fetch and decode. 683 cpu->removeInstsUntil(seq_num, tid); 684} 685 686template<class Impl> 687bool --- 58 unchanged lines hidden (view full) --- 746 cpu->deactivateStage(O3CPU::FetchIdx); 747 } 748 749 return Inactive; 750} 751 752template <class Impl> 753void |
754DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, |
755 const InstSeqNum &seq_num, ThreadID tid) 756{ |
757 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); |
758 |
759 doSquash(newPC, tid); |
760 761 // Tell the CPU to remove any instructions that are not in the ROB. 762 cpu->removeInstsNotInROB(tid); 763} 764 765template <class Impl> 766void 767DefaultFetch<Impl>::tick() --- 96 unchanged lines hidden (view full) --- 864 } 865 866 // Check squash signals from commit. 867 if (fromCommit->commitInfo[tid].squash) { 868 869 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 870 "from commit.\n",tid); 871 // In any case, squash. |
872 squash(fromCommit->commitInfo[tid].pc, |
873 fromCommit->commitInfo[tid].doneSeqNum, 874 tid); 875 876 // Also check if there's a mispredict that happened. 877 if (fromCommit->commitInfo[tid].branchMispredict) { 878 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, |
879 fromCommit->commitInfo[tid].pc, |
880 fromCommit->commitInfo[tid].branchTaken, 881 tid); 882 } else { 883 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 884 tid); 885 } 886 887 return true; --- 26 unchanged lines hidden (view full) --- 914 tid); 915 } else { 916 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 917 tid); 918 } 919 920 if (fetchStatus[tid] != Squashing) { 921 |
922 TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC; 923 DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC); |
924 // Squash unless we're already squashing 925 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, |
926 fromDecode->decodeInfo[tid].doneSeqNum, 927 tid); 928 929 return true; 930 } 931 } 932 933 if (checkStall(tid) && --- 38 unchanged lines hidden (view full) --- 972 // Breaks looping condition in tick() 973 threadFetched = numFetchingThreads; 974 return; 975 } 976 977 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 978 979 // The current PC. |
980 TheISA::PCState fetchPC = pc[tid]; |
981 982 // Fault code for memory access. 983 Fault fault = NoFault; 984 985 // If returning from the delay of a cache miss, then update the status 986 // to running, otherwise do the cache access. Possibly move this up 987 // to tick() function. 988 if (fetchStatus[tid] == IcacheAccessComplete) { 989 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", 990 tid); 991 992 fetchStatus[tid] = Running; 993 status_change = true; 994 } else if (fetchStatus[tid] == Running) { 995 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " |
996 "instruction, starting at PC %s.\n", tid, fetchPC); |
997 |
998 bool fetch_success = fetchCacheLine(fetchPC.instAddr(), fault, tid); |
999 if (!fetch_success) { 1000 if (cacheBlocked) { 1001 ++icacheStallCycles; 1002 } else { 1003 ++fetchMiscStallCycles; 1004 } 1005 return; 1006 } --- 21 unchanged lines hidden (view full) --- 1028 1029 // If we had a stall due to an icache miss, then return. 1030 if (fetchStatus[tid] == IcacheWaitResponse) { 1031 ++icacheStallCycles; 1032 status_change = true; 1033 return; 1034 } 1035 |
1036 TheISA::PCState nextPC = fetchPC; |
1037 1038 InstSeqNum inst_seq; 1039 MachInst inst; 1040 ExtMachInst ext_inst; |
1041 1042 StaticInstPtr staticInst = NULL; 1043 StaticInstPtr macroop = NULL; 1044 1045 if (fault == NoFault) { |
1046 //XXX Masking out pal mode bit. This will break x86. Alpha needs 1047 //to pull the pal mode bit ouf ot the instruction address. 1048 unsigned offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid]; 1049 assert(offset < cacheBlkSize); 1050 |
1051 // If the read of the first instruction was successful, then grab the 1052 // instructions from the rest of the cache line and put them into the 1053 // queue heading to decode. 1054 1055 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1056 "decode.\n",tid); 1057 1058 // Need to keep track of whether or not a predicted branch 1059 // ended this fetch block. 1060 bool predicted_branch = false; 1061 1062 while (offset < cacheBlkSize && 1063 numInst < fetchWidth && 1064 !predicted_branch) { 1065 |
1066 // Make sure this is a valid index. 1067 assert(offset <= cacheBlkSize - instSize); 1068 1069 if (!macroop) { 1070 // Get the instruction from the array of the cache line. 1071 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1072 (&cacheData[tid][offset])); 1073 1074 predecoder.setTC(cpu->thread[tid]->getTC()); |
1075 predecoder.moreBytes(fetchPC, fetchPC.instAddr(), inst); |
1076 |
1077 ext_inst = predecoder.getExtMachInst(fetchPC); 1078 staticInst = StaticInstPtr(ext_inst, fetchPC.instAddr()); |
1079 if (staticInst->isMacroop()) 1080 macroop = staticInst; 1081 } 1082 do { 1083 if (macroop) { |
1084 staticInst = macroop->fetchMicroop(fetchPC.microPC()); |
1085 if (staticInst->isLastMicroop()) 1086 macroop = NULL; 1087 } 1088 1089 // Get a sequence number. 1090 inst_seq = cpu->getAndIncrementInstSeq(); 1091 1092 // Create a new DynInst from the instruction fetched. 1093 DynInstPtr instruction = new DynInst(staticInst, |
1094 fetchPC, nextPC, |
1095 inst_seq, cpu); 1096 instruction->setTid(tid); 1097 1098 instruction->setASID(tid); 1099 1100 instruction->setThreadState(cpu->thread[tid]); 1101 |
1102 DPRINTF(Fetch, "[tid:%i]: Instruction PC %s (%d) created " 1103 "[sn:%lli]\n", tid, instruction->pcState(), 1104 instruction->microPC(), inst_seq); |
1105 1106 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); 1107 |
1108 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, 1109 instruction->staticInst-> 1110 disassemble(fetchPC.instAddr())); |
1111 1112#if TRACING_ON 1113 instruction->traceData = 1114 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid), |
1115 instruction->staticInst, fetchPC, macroop); |
1116#else 1117 instruction->traceData = NULL; 1118#endif 1119 |
1120 // If we're branching after this instruction, quite fetching 1121 // from the same block then. 1122 predicted_branch = fetchPC.branching(); |
1123 predicted_branch |= |
1124 lookupAndUpdateNextPC(instruction, nextPC); 1125 if (predicted_branch) { 1126 DPRINTF(Fetch, "Branch detected with PC = %s\n", fetchPC); 1127 } |
1128 1129 // Add instruction to the CPU's list of instructions. 1130 instruction->setInstListIt(cpu->addInst(instruction)); 1131 1132 // Write the instruction to the first slot in the queue 1133 // that heads to decode. 1134 toDecode->insts[numInst] = instruction; 1135 1136 toDecode->size++; 1137 1138 // Increment stat of fetched instructions. 1139 ++fetchedInsts; 1140 1141 // Move to the next instruction, unless we have a branch. |
1142 fetchPC = nextPC; |
1143 1144 if (instruction->isQuiesce()) { 1145 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1146 curTick); 1147 fetchStatus[tid] = QuiescePending; 1148 ++numInst; 1149 status_change = true; 1150 break; 1151 } 1152 1153 ++numInst; 1154 } while (staticInst->isMicroop() && 1155 !staticInst->isLastMicroop() && 1156 numInst < fetchWidth); |
1157 //XXX Masking out pal mode bit. 1158 offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid]; |
1159 } 1160 1161 if (predicted_branch) { 1162 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1163 "instruction encountered.\n", tid); 1164 } else if (numInst >= fetchWidth) { 1165 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1166 "for this cycle.\n", tid); --- 5 unchanged lines hidden (view full) --- 1172 1173 if (numInst > 0) { 1174 wroteToTimeBuffer = true; 1175 } 1176 1177 // Now that fetching is completed, update the PC to signify what the next 1178 // cycle will be. 1179 if (fault == NoFault) { |
1180 pc[tid] = nextPC; 1181 DPRINTF(Fetch, "[tid:%i]: Setting PC to %s.\n", tid, nextPC); |
1182 } else { 1183 // We shouldn't be in an icache miss and also have a fault (an ITB 1184 // miss) 1185 if (fetchStatus[tid] == IcacheWaitResponse) { 1186 panic("Fetch should have exited prior to this!"); 1187 } 1188 1189 // Send the fault to commit. This thread will not do anything 1190 // until commit handles the fault. The only other way it can 1191 // wake up is if a squash comes along and changes the PC. 1192 assert(numInst < fetchWidth); 1193 // Get a sequence number. 1194 inst_seq = cpu->getAndIncrementInstSeq(); 1195 // We will use a nop in order to carry the fault. 1196 ext_inst = TheISA::NoopMachInst; 1197 1198 // Create a new DynInst from the dummy nop. |
1199 DynInstPtr instruction = new DynInst(ext_inst, fetchPC, nextPC, |
1200 inst_seq, cpu); |
1201 TheISA::advancePC(nextPC, instruction->staticInst); 1202 instruction->setPredTarg(nextPC); |
1203 instruction->setTid(tid); 1204 1205 instruction->setASID(tid); 1206 1207 instruction->setThreadState(cpu->thread[tid]); 1208 1209 instruction->traceData = NULL; 1210 --- 6 unchanged lines hidden (view full) --- 1217 1218 wroteToTimeBuffer = true; 1219 1220 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1221 1222 fetchStatus[tid] = TrapPending; 1223 status_change = true; 1224 |
1225 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s", 1226 tid, fault->name(), pc[tid]); |
1227 } 1228} 1229 1230template<class Impl> 1231void 1232DefaultFetch<Impl>::recvRetry() 1233{ 1234 if (retryPkt != NULL) { --- 169 unchanged lines hidden --- |