1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 585 unchanged lines hidden (view full) --- 594 // Build request here. 595 RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, 596 fetch_PC, cpu->thread[tid]->contextId(), 597 tid); 598 599 memReq[tid] = mem_req; 600 601 // Translate the instruction request. |
602 fault = cpu->itb->translate(mem_req, cpu->thread[tid]->getTC()); |
603 604 // In the case of faults, the fetch stage may need to stall and wait 605 // for the ITB miss to be handled. 606 607 // If translation was successful, attempt to read the first 608 // instruction. 609 if (fault == NoFault) { 610#if 0 --- 833 unchanged lines hidden --- |