1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 |
32#include "config/use_checker.hh" 33 34#include "arch/isa_traits.hh" 35#include "arch/utility.hh" 36#include "cpu/checker/cpu.hh" 37#include "cpu/exetrace.hh" 38#include "cpu/o3/fetch.hh" 39#include "mem/packet.hh" 40#include "mem/request.hh" 41#include "sim/byteswap.hh" 42#include "sim/host.hh" 43#include "sim/core.hh" 44 45#if FULL_SYSTEM 46#include "arch/tlb.hh" 47#include "arch/vtophys.hh" 48#include "sim/system.hh" 49#endif // FULL_SYSTEM 50 |
51#include <algorithm> 52 |
53template<class Impl> 54void 55DefaultFetch<Impl>::IcachePort::setPeer(Port *port) 56{ 57 Port::setPeer(port); 58 59 fetch->setIcache(); 60} --- 308 unchanged lines hidden (view full) --- 369 pkt->req != memReq[tid] || 370 isSwitchedOut()) { 371 ++fetchIcacheSquashes; 372 delete pkt->req; 373 delete pkt; 374 return; 375 } 376 |
377 memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize); |
378 cacheDataValid[tid] = true; 379 380 if (!drainPending) { 381 // Wake up the CPU (if it went to sleep and was waiting on 382 // this completion event). 383 cpu->wakeCPU(); 384 385 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", --- 383 unchanged lines hidden (view full) --- 769 } 770 771 return Inactive; 772} 773 774template <class Impl> 775void 776DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC, |
777 const InstSeqNum &seq_num, unsigned tid) |
778{ 779 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 780 781 doSquash(new_PC, new_NPC, tid); 782 |
783 // Tell the CPU to remove any instructions that are not in the ROB. |
784 cpu->removeInstsNotInROB(tid); |
785} 786 787template <class Impl> 788void 789DefaultFetch<Impl>::tick() 790{ 791 std::list<unsigned>::iterator threads = activeThreads->begin(); 792 std::list<unsigned>::iterator end = activeThreads->end(); --- 92 unchanged lines hidden (view full) --- 885 stalls[tid].commit = false; 886 } 887 888 // Check squash signals from commit. 889 if (fromCommit->commitInfo[tid].squash) { 890 891 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 892 "from commit.\n",tid); |
893 // In any case, squash. 894 squash(fromCommit->commitInfo[tid].nextPC, 895 fromCommit->commitInfo[tid].nextNPC, |
896 fromCommit->commitInfo[tid].doneSeqNum, |
897 tid); 898 899 // Also check if there's a mispredict that happened. 900 if (fromCommit->commitInfo[tid].branchMispredict) { 901 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 902 fromCommit->commitInfo[tid].nextPC, 903 fromCommit->commitInfo[tid].branchTaken, 904 tid); --- 32 unchanged lines hidden (view full) --- 937 tid); 938 } else { 939 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 940 tid); 941 } 942 943 if (fetchStatus[tid] != Squashing) { 944 |
945 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n", 946 fromDecode->decodeInfo[tid].nextPC, 947 fromDecode->decodeInfo[tid].nextNPC); 948 // Squash unless we're already squashing 949 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 950 fromDecode->decodeInfo[tid].nextNPC, |
951 fromDecode->decodeInfo[tid].doneSeqNum, |
952 tid); 953 954 return true; 955 } 956 } 957 958 if (checkStall(tid) && 959 fetchStatus[tid] != IcacheWaitResponse && --- 144 unchanged lines hidden (view full) --- 1104 // Make sure this is a valid index. 1105 assert(offset <= cacheBlkSize - instSize); 1106 1107 // Get the instruction from the array of the cache line. 1108 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1109 (&cacheData[tid][offset])); 1110 1111 predecoder.setTC(cpu->thread[tid]->getTC()); |
1112 predecoder.moreBytes(fetch_PC, 0, inst); |
1113 1114 ext_inst = predecoder.getExtMachInst(); 1115 1116 // Create a new DynInst from the instruction fetched. 1117 DynInstPtr instruction = new DynInst(ext_inst, 1118 fetch_PC, fetch_NPC, 1119 next_PC, next_NPC, 1120 inst_seq, cpu); --- 7 unchanged lines hidden (view full) --- 1128 "[sn:%lli]\n", 1129 tid, instruction->readPC(), inst_seq); 1130 1131 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); 1132 1133 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1134 tid, instruction->staticInst->disassemble(fetch_PC)); 1135 |
1136 instruction->traceData = 1137 Trace::getInstRecord(curTick, cpu->tcBase(tid), 1138 instruction->staticInst, 1139 instruction->readPC()); |
1140 1141 ///FIXME This needs to be more robust in dealing with delay slots |
1142 lookupAndUpdateNextPC(instruction, next_PC, next_NPC); 1143 predicted_branch |= (next_PC != fetch_NPC); 1144 1145 // Add instruction to the CPU's list of instructions. 1146 instruction->setInstListIt(cpu->addInst(instruction)); 1147 1148 // Write the instruction to the first slot in the queue 1149 // that heads to decode. --- 37 unchanged lines hidden (view full) --- 1187 } 1188 1189 // Now that fetching is completed, update the PC to signify what the next 1190 // cycle will be. 1191 if (fault == NoFault) { 1192 PC[tid] = next_PC; 1193 nextPC[tid] = next_NPC; 1194 nextNPC[tid] = next_NPC + instSize; |
1195 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC); |
1196 } else { 1197 // We shouldn't be in an icache miss and also have a fault (an ITB 1198 // miss) 1199 if (fetchStatus[tid] == IcacheWaitResponse) { 1200 panic("Fetch should have exited prior to this!"); 1201 } 1202 1203 // Send the fault to commit. This thread will not do anything --- 217 unchanged lines hidden --- |