1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 1114 unchanged lines hidden (view full) --- 1123 // Make sure this is a valid index. 1124 assert(offset <= cacheBlkSize - instSize); 1125 1126 // Get the instruction from the array of the cache line. 1127 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1128 (&cacheData[tid][offset])); 1129 1130 predecoder.setTC(cpu->thread[tid]->getTC()); |
1131 predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst); |
1132 1133 ext_inst = predecoder.getExtMachInst(); 1134 1135 // Create a new DynInst from the instruction fetched. 1136 DynInstPtr instruction = new DynInst(ext_inst, 1137 fetch_PC, fetch_NPC, 1138 next_PC, next_NPC, 1139 inst_seq, cpu); --- 311 unchanged lines hidden --- |