1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 26 unchanged lines hidden (view full) --- 35#include "arch/utility.hh" 36#include "cpu/checker/cpu.hh" 37#include "cpu/exetrace.hh" 38#include "cpu/o3/fetch.hh" 39#include "mem/packet.hh" 40#include "mem/request.hh" 41#include "sim/byteswap.hh" 42#include "sim/host.hh" |
43#include "sim/core.hh" |
44 45#if FULL_SYSTEM 46#include "arch/tlb.hh" 47#include "arch/vtophys.hh" 48#include "sim/system.hh" 49#endif // FULL_SYSTEM 50 51#include <algorithm> --- 545 unchanged lines hidden (view full) --- 597 memReq[tid]->paddr); 598 ret_fault = TheISA::genMachineCheckFault(); 599 return false; 600 } 601#endif 602 603 // Build packet here. 604 PacketPtr data_pkt = new Packet(mem_req, |
605 MemCmd::ReadReq, Packet::Broadcast); |
606 data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 607 608 cacheDataPC[tid] = block_PC; 609 cacheDataValid[tid] = false; 610 611 DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 612 613 fetchedCacheLines++; 614 615 // Now do the timing access to see whether or not the instruction 616 // exists within the cache. 617 if (!icachePort->sendTiming(data_pkt)) { 618 if (data_pkt->result == Packet::BadAddress) { 619 fault = TheISA::genMachineCheckFault(); 620 delete mem_req; 621 memReq[tid] = NULL; |
622 } 623 assert(retryPkt == NULL); 624 assert(retryTid == -1); 625 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 626 fetchStatus[tid] = IcacheWaitRetry; 627 retryPkt = data_pkt; 628 retryTid = tid; 629 cacheBlocked = true; --- 34 unchanged lines hidden (view full) --- 664 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 665 tid); 666 memReq[tid] = NULL; 667 } 668 669 // Get rid of the retrying packet if it was from this thread. 670 if (retryTid == tid) { 671 assert(cacheBlocked); |
672 cacheBlocked = false; |
673 retryTid = -1; |
674 delete retryPkt->req; 675 delete retryPkt; 676 retryPkt = NULL; |
677 } 678 679 fetchStatus[tid] = Squashing; 680 681 ++fetchSquashCycles; 682} 683 684template<class Impl> --- 462 unchanged lines hidden (view full) --- 1147 1148 instruction->traceData = 1149 Trace::getInstRecord(curTick, cpu->tcBase(tid), 1150 instruction->staticInst, 1151 instruction->readPC()); 1152 1153 ///FIXME This needs to be more robust in dealing with delay slots 1154#if !ISA_HAS_DELAY_SLOT |
1155 predicted_branch |= |
1156#endif 1157 lookupAndUpdateNextPC(instruction, next_PC, next_NPC); 1158 predicted_branch |= (next_PC != fetch_NPC); 1159 1160 // Add instruction to the CPU's list of instructions. 1161 instruction->setInstListIt(cpu->addInst(instruction)); 1162 1163 // Write the instruction to the first slot in the queue --- 54 unchanged lines hidden (view full) --- 1218 if (fetchStatus[tid] == IcacheWaitResponse) { 1219 panic("Fetch should have exited prior to this!"); 1220 } 1221 1222 // Send the fault to commit. This thread will not do anything 1223 // until commit handles the fault. The only other way it can 1224 // wake up is if a squash comes along and changes the PC. 1225#if FULL_SYSTEM |
1226 assert(numInst != fetchWidth); |
1227 // Get a sequence number. 1228 inst_seq = cpu->getAndIncrementInstSeq(); 1229 // We will use a nop in order to carry the fault. 1230 ext_inst = TheISA::NoopMachInst; 1231 1232 // Create a new DynInst from the dummy nop. 1233 DynInstPtr instruction = new DynInst(ext_inst, 1234 fetch_PC, fetch_NPC, --- 205 unchanged lines hidden --- |