1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 327 unchanged lines hidden (view full) --- 336 337 memReq[tid] = NULL; 338 339 // Create space to store a cache line. 340 cacheData[tid] = new uint8_t[cacheBlkSize]; 341 cacheDataPC[tid] = 0; 342 cacheDataValid[tid] = false; 343 |
344 stalls[tid].decode = false; 345 stalls[tid].rename = false; 346 stalls[tid].iew = false; 347 stalls[tid].commit = false; 348 } 349} 350 351template<class Impl> --- 77 unchanged lines hidden (view full) --- 429 stalls[i].decode = 0; 430 stalls[i].rename = 0; 431 stalls[i].iew = 0; 432 stalls[i].commit = 0; 433 PC[i] = cpu->readPC(i); 434 nextPC[i] = cpu->readNextPC(i); 435#if ISA_HAS_DELAY_SLOT 436 nextNPC[i] = cpu->readNextNPC(i); |
437#else 438 nextNPC[i] = nextPC[i] + sizeof(TheISA::MachInst); |
439#endif 440 fetchStatus[i] = Running; 441 } 442 numInst = 0; 443 wroteToTimeBuffer = false; 444 _status = Inactive; 445 switchedOut = false; 446 interruptPending = false; --- 42 unchanged lines hidden (view full) --- 489 Addr &next_NPC) 490{ 491 // Do branch prediction check here. 492 // A bit of a misnomer...next_PC is actually the current PC until 493 // this function updates it. 494 bool predict_taken; 495 496 if (!inst->isControl()) { |
497 next_PC = next_NPC; 498 next_NPC = next_NPC + instSize; 499 inst->setPredTarg(next_PC, next_NPC); |
500 inst->setPredTaken(false); 501 return false; 502 } 503 504 int tid = inst->threadNumber; |
505 Addr pred_PC = next_PC; 506 predict_taken = branchPred.predict(inst, pred_PC, tid); 507 |
508/* if (predict_taken) { 509 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n", 510 tid, pred_PC); |
511 } else { 512 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); |
513 }*/ |
514 |
515#if ISA_HAS_DELAY_SLOT |
516 next_PC = next_NPC; |
517 if (predict_taken) |
518 next_NPC = pred_PC; |
519 else 520 next_NPC += instSize; |
521#else |
522 if (predict_taken) 523 next_PC = pred_PC; 524 else 525 next_PC += instSize; 526 next_NPC = next_PC + instSize; |
527#endif |
528/* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", 529 tid, next_PC, next_NPC);*/ |
530 inst->setPredTarg(next_PC, next_NPC); 531 inst->setPredTaken(predict_taken); 532 533 ++fetchedBranches; 534 535 if (predict_taken) { 536 ++predictedBranches; 537 } --- 148 unchanged lines hidden (view full) --- 686DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC, 687 const InstSeqNum &seq_num, 688 unsigned tid) 689{ 690 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 691 692 doSquash(new_PC, new_NPC, tid); 693 |
694 // Tell the CPU to remove any instructions that are in flight between 695 // fetch and decode. 696 cpu->removeInstsUntil(seq_num, tid); 697} 698 699template<class Impl> 700bool 701DefaultFetch<Impl>::checkStall(unsigned tid) const --- 66 unchanged lines hidden (view full) --- 768 const InstSeqNum &seq_num, 769 bool squash_delay_slot, unsigned tid) 770{ 771 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 772 773 doSquash(new_PC, new_NPC, tid); 774 775#if ISA_HAS_DELAY_SLOT |
776 // Tell the CPU to remove any instructions that are not in the ROB. 777 cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num); 778#else 779 // Tell the CPU to remove any instructions that are not in the ROB. 780 cpu->removeInstsNotInROB(tid, true, 0); 781#endif 782} 783 --- 161 unchanged lines hidden (view full) --- 945 946 if (fetchStatus[tid] != Squashing) { 947 948#if ISA_HAS_DELAY_SLOT 949 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum; 950#else 951 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum; 952#endif |
953 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n", 954 fromDecode->decodeInfo[tid].nextPC, 955 fromDecode->decodeInfo[tid].nextNPC); |
956 // Squash unless we're already squashing 957 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 958 fromDecode->decodeInfo[tid].nextNPC, 959 doneSeqNum, 960 tid); 961 962 return true; 963 } --- 131 unchanged lines hidden (view full) --- 1095 numInst < fetchWidth && 1096 !predicted_branch; 1097 ++numInst) { 1098 1099 // If we're branching after this instruction, quite fetching 1100 // from the same block then. 1101 predicted_branch = 1102 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC); |
1103 if (predicted_branch) { 1104 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n", 1105 fetch_PC, fetch_NPC); 1106 } |
1107 |
1108 |
1109 // Get a sequence number. 1110 inst_seq = cpu->getAndIncrementInstSeq(); 1111 1112 // Make sure this is a valid index. 1113 assert(offset <= cacheBlkSize - instSize); 1114 1115 // Get the instruction from the array of the cache line. 1116 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> --- 17 unchanged lines hidden (view full) --- 1134 instruction->setASID(tid); 1135 1136 instruction->setThreadState(cpu->thread[tid]); 1137 1138 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1139 "[sn:%lli]\n", 1140 tid, instruction->readPC(), inst_seq); 1141 |
1142 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); |
1143 1144 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1145 tid, instruction->staticInst->disassemble(fetch_PC)); 1146 1147 instruction->traceData = 1148 Trace::getInstRecord(curTick, cpu->tcBase(tid), 1149 instruction->staticInst, 1150 instruction->readPC()); 1151 1152 lookupAndUpdateNextPC(instruction, next_PC, next_NPC); |
1153 predicted_branch |= (next_PC != fetch_NPC); |
1154 1155 // Add instruction to the CPU's list of instructions. 1156 instruction->setInstListIt(cpu->addInst(instruction)); 1157 1158 // Write the instruction to the first slot in the queue 1159 // that heads to decode. 1160 toDecode->insts[numInst] = instruction; 1161 --- 32 unchanged lines hidden (view full) --- 1194 1195 if (numInst > 0) { 1196 wroteToTimeBuffer = true; 1197 } 1198 1199 // Now that fetching is completed, update the PC to signify what the next 1200 // cycle will be. 1201 if (fault == NoFault) { |
1202 PC[tid] = next_PC; 1203 nextPC[tid] = next_NPC; 1204 nextNPC[tid] = next_NPC + instSize; |
1205#if ISA_HAS_DELAY_SLOT |
1206 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]); 1207#else |
1208 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC); |
1209#endif 1210 } else { 1211 // We shouldn't be in an icache miss and also have a fault (an ITB 1212 // miss) 1213 if (fetchStatus[tid] == IcacheWaitResponse) { 1214 panic("Fetch should have exited prior to this!"); 1215 } 1216 --- 212 unchanged lines hidden --- |