1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 305 unchanged lines hidden (view full) --- 314template<class Impl> 315void 316DefaultFetch<Impl>::initStage() 317{ 318 // Setup PC and nextPC with initial state. 319 for (int tid = 0; tid < numThreads; tid++) { 320 PC[tid] = cpu->readPC(tid); 321 nextPC[tid] = cpu->readNextPC(tid); |
322 nextNPC[tid] = cpu->readNextNPC(tid); |
323 } 324 325 // Size of cache block. 326 cacheBlkSize = icachePort->peerBlockSize(); 327 328 // Create mask to get rid of offset bits. 329 cacheBlkMask = (cacheBlkSize - 1); 330 --- 166 unchanged lines hidden (view full) --- 497{ 498 // Do branch prediction check here. 499 // A bit of a misnomer...next_PC is actually the current PC until 500 // this function updates it. 501 bool predict_taken; 502 503 if (!inst->isControl()) { 504#if ISA_HAS_DELAY_SLOT |
505 next_PC = next_NPC; 506 next_NPC = next_NPC + instSize; 507 inst->setPredTarg(next_PC, next_NPC); |
508#else 509 next_PC = next_PC + instSize; |
510 inst->setPredTarg(next_PC, next_PC + sizeof(TheISA::MachInst)); |
511#endif |
512 inst->setPredTaken(false); |
513 return false; 514 } 515 516 int tid = inst->threadNumber; 517#if ISA_HAS_DELAY_SLOT 518 Addr pred_PC = next_PC; 519 predict_taken = branchPred.predict(inst, pred_PC, tid); 520 521 if (predict_taken) { |
522 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken.\n", tid); |
523 } else { |
524 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); |
525 } 526 |
527 next_PC = next_NPC; |
528 if (predict_taken) { |
529 next_NPC = pred_PC; |
530 // Update delay slot info 531 ++delaySlotInfo[tid].numInsts; 532 delaySlotInfo[tid].targetAddr = pred_PC; 533 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid, 534 delaySlotInfo[tid].numInsts); |
535 } else { |
536 next_NPC = next_NPC + instSize; 537 } 538#else 539 predict_taken = branchPred.predict(inst, next_PC, tid); 540#endif |
541 DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", 542 tid, next_PC, next_NPC); 543 inst->setPredTarg(next_PC, next_NPC); 544 inst->setPredTaken(predict_taken); |
545 546 ++fetchedBranches; 547 548 if (predict_taken) { 549 ++predictedBranches; 550 } 551 552 return predict_taken; --- 104 unchanged lines hidden (view full) --- 657 } 658 659 ret_fault = fault; 660 return true; 661} 662 663template <class Impl> 664inline void |
665DefaultFetch 666 const Addr &new_NPC, unsigned tid) |
667{ |
668 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n", 669 tid, new_PC, new_NPC); |
670 671 PC[tid] = new_PC; |
672 nextPC[tid] = new_NPC; 673 nextNPC[tid] = new_NPC + instSize; |
674 675 // Clear the icache miss if it's outstanding. 676 if (fetchStatus[tid] == IcacheWaitResponse) { 677 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 678 tid); 679 memReq[tid] = NULL; 680 } 681 --- 9 unchanged lines hidden (view full) --- 691 692 fetchStatus[tid] = Squashing; 693 694 ++fetchSquashCycles; 695} 696 697template<class Impl> 698void |
699DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC, |
700 const InstSeqNum &seq_num, 701 unsigned tid) 702{ 703 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 704 |
705 doSquash(new_PC, new_NPC, tid); |
706 707#if ISA_HAS_DELAY_SLOT 708 if (seq_num <= delaySlotInfo[tid].branchSeqNum) { 709 delaySlotInfo[tid].numInsts = 0; 710 delaySlotInfo[tid].targetAddr = 0; 711 delaySlotInfo[tid].targetReady = false; 712 } 713#endif --- 29 unchanged lines hidden (view full) --- 743 return ret_val; 744} 745 746template<class Impl> 747typename DefaultFetch<Impl>::FetchStatus 748DefaultFetch<Impl>::updateFetchStatus() 749{ 750 //Check Running |
751 std::list<unsigned>::iterator threads = (*activeThreads).begin(); |
752 |
753 while (threads != (*activeThreads).end()) { 754 |
755 unsigned tid = *threads++; 756 757 if (fetchStatus[tid] == Running || 758 fetchStatus[tid] == Squashing || 759 fetchStatus[tid] == IcacheAccessComplete) { 760 761 if (_status == Inactive) { 762 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); --- 17 unchanged lines hidden (view full) --- 780 cpu->deactivateStage(O3CPU::FetchIdx); 781 } 782 783 return Inactive; 784} 785 786template <class Impl> 787void |
788DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC, 789 const InstSeqNum &seq_num, |
790 bool squash_delay_slot, unsigned tid) 791{ 792 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 793 |
794 doSquash(new_PC, new_NPC, tid); |
795 796#if ISA_HAS_DELAY_SLOT 797 if (seq_num <= delaySlotInfo[tid].branchSeqNum) { 798 delaySlotInfo[tid].numInsts = 0; 799 delaySlotInfo[tid].targetAddr = 0; 800 delaySlotInfo[tid].targetReady = false; 801 } 802 --- 4 unchanged lines hidden (view full) --- 807 cpu->removeInstsNotInROB(tid, true, 0); 808#endif 809} 810 811template <class Impl> 812void 813DefaultFetch<Impl>::tick() 814{ |
815 std::list<unsigned>::iterator threads = (*activeThreads).begin(); |
816 bool status_change = false; 817 818 wroteToTimeBuffer = false; 819 |
820 while (threads != (*activeThreads).end()) { |
821 unsigned tid = *threads++; 822 823 // Check the signals for each thread to determine the proper status 824 // for each thread. 825 bool updated_status = checkSignalsAndUpdate(tid); 826 status_change = status_change || updated_status; 827 } 828 --- 87 unchanged lines hidden (view full) --- 916 917#if ISA_HAS_DELAY_SLOT 918 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 919#else 920 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum; 921#endif 922 // In any case, squash. 923 squash(fromCommit->commitInfo[tid].nextPC, |
924 fromCommit->commitInfo[tid].nextNPC, |
925 doneSeqNum, 926 fromCommit->commitInfo[tid].squashDelaySlot, 927 tid); 928 929 // Also check if there's a mispredict that happened. 930 if (fromCommit->commitInfo[tid].branchMispredict) { 931 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 932 fromCommit->commitInfo[tid].nextPC, --- 41 unchanged lines hidden (view full) --- 974 975#if ISA_HAS_DELAY_SLOT 976 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum; 977#else 978 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum; 979#endif 980 // Squash unless we're already squashing 981 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, |
982 fromDecode->decodeInfo[tid].nextNPC, |
983 doneSeqNum, 984 tid); 985 986 return true; 987 } 988 } 989 990 if (checkStall(tid) && --- 40 unchanged lines hidden (view full) --- 1031 return; 1032 } 1033 1034 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1035 1036 // The current PC. 1037 Addr &fetch_PC = PC[tid]; 1038 |
1039 Addr &fetch_NPC = nextPC[tid]; 1040 |
1041 // Fault code for memory access. 1042 Fault fault = NoFault; 1043 1044 // If returning from the delay of a cache miss, then update the status 1045 // to running, otherwise do the cache access. Possibly move this up 1046 // to tick() function. 1047 if (fetchStatus[tid] == IcacheAccessComplete) { 1048 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", --- 40 unchanged lines hidden (view full) --- 1089 // If we had a stall due to an icache miss, then return. 1090 if (fetchStatus[tid] == IcacheWaitResponse) { 1091 ++icacheStallCycles; 1092 status_change = true; 1093 return; 1094 } 1095 1096 Addr next_PC = fetch_PC; |
1097 Addr next_NPC = fetch_NPC; 1098 |
1099 InstSeqNum inst_seq; 1100 MachInst inst; 1101 ExtMachInst ext_inst; 1102 // @todo: Fix this hack. 1103 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; 1104 1105 if (fault == NoFault) { 1106 // If the read of the first instruction was successful, then grab the 1107 // instructions from the rest of the cache line and put them into the 1108 // queue heading to decode. 1109 1110 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1111 "decode.\n",tid); 1112 1113 // Need to keep track of whether or not a predicted branch 1114 // ended this fetch block. 1115 bool predicted_branch = false; 1116 |
1117 for (; 1118 offset < cacheBlkSize && 1119 numInst < fetchWidth && |
1120 !predicted_branch; |
1121 ++numInst) { 1122 |
1123 // If we're branching after this instruction, quite fetching 1124 // from the same block then. 1125 predicted_branch = 1126 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC); 1127 |
1128 // Get a sequence number. 1129 inst_seq = cpu->getAndIncrementInstSeq(); 1130 1131 // Make sure this is a valid index. 1132 assert(offset <= cacheBlkSize - instSize); 1133 1134 // Get the instruction from the array of the cache line. 1135 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1136 (&cacheData[tid][offset])); 1137 1138#if THE_ISA == ALPHA_ISA 1139 ext_inst = TheISA::makeExtMI(inst, fetch_PC); 1140#elif THE_ISA == SPARC_ISA 1141 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); 1142#elif THE_ISA == MIPS_ISA 1143 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); 1144#endif 1145 1146 // Create a new DynInst from the instruction fetched. |
1147 DynInstPtr instruction = new DynInst(ext_inst, 1148 fetch_PC, fetch_NPC, 1149 next_PC, next_NPC, |
1150 inst_seq, cpu); 1151 instruction->setTid(tid); 1152 1153 instruction->setASID(tid); 1154 1155 instruction->setThreadState(cpu->thread[tid]); 1156 1157 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1158 "[sn:%lli]\n", 1159 tid, instruction->readPC(), inst_seq); 1160 |
1161 DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); 1162 |
1163 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1164 tid, instruction->staticInst->disassemble(fetch_PC)); 1165 1166 instruction->traceData = 1167 Trace::getInstRecord(curTick, cpu->tcBase(tid), 1168 instruction->staticInst, 1169 instruction->readPC()); 1170 |
1171 lookupAndUpdateNextPC(instruction, next_PC, next_NPC); |
1172 1173 // Add instruction to the CPU's list of instructions. 1174 instruction->setInstListIt(cpu->addInst(instruction)); 1175 1176 // Write the instruction to the first slot in the queue 1177 // that heads to decode. 1178 toDecode->insts[numInst] = instruction; 1179 1180 toDecode->size++; 1181 1182 // Increment stat of fetched instructions. 1183 ++fetchedInsts; 1184 1185 // Move to the next instruction, unless we have a branch. 1186 fetch_PC = next_PC; |
1187 fetch_NPC = next_NPC; |
1188 1189 if (instruction->isQuiesce()) { 1190 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1191 curTick); 1192 fetchStatus[tid] = QuiescePending; 1193 ++numInst; 1194 status_change = true; 1195 break; 1196 } 1197 1198 offset += instSize; |
1199 } 1200 1201 if (offset >= cacheBlkSize) { 1202 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1203 "block.\n", tid); 1204 } else if (numInst >= fetchWidth) { 1205 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1206 "for this cycle.\n", tid); |
1207 } else if (predicted_branch) { |
1208 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1209 "instruction encountered.\n", tid); 1210 } 1211 } 1212 1213 if (numInst > 0) { 1214 wroteToTimeBuffer = true; 1215 } 1216 1217 // Now that fetching is completed, update the PC to signify what the next 1218 // cycle will be. 1219 if (fault == NoFault) { 1220#if ISA_HAS_DELAY_SLOT 1221 if (delaySlotInfo[tid].targetReady && 1222 delaySlotInfo[tid].numInsts == 0) { 1223 // Set PC to target |
1224 PC[tid] = next_PC; 1225 nextPC[tid] = next_NPC; 1226 nextNPC[tid] = next_NPC + instSize; |
1227 1228 delaySlotInfo[tid].targetReady = false; 1229 } else { 1230 PC[tid] = next_PC; 1231 nextPC[tid] = next_NPC; 1232 nextNPC[tid] = next_NPC + instSize; 1233 } 1234 --- 16 unchanged lines hidden (view full) --- 1251#if FULL_SYSTEM 1252 assert(numInst != fetchWidth); 1253 // Get a sequence number. 1254 inst_seq = cpu->getAndIncrementInstSeq(); 1255 // We will use a nop in order to carry the fault. 1256 ext_inst = TheISA::NoopMachInst; 1257 1258 // Create a new DynInst from the dummy nop. |
1259 DynInstPtr instruction = new DynInst(ext_inst, 1260 fetch_PC, fetch_NPC, 1261 next_PC, next_NPC, |
1262 inst_seq, cpu); |
1263 instruction->setPredTarg(next_PC, next_NPC); |
1264 instruction->setTid(tid); 1265 1266 instruction->setASID(tid); 1267 1268 instruction->setThreadState(cpu->thread[tid]); 1269 1270 instruction->traceData = NULL; 1271 --- 67 unchanged lines hidden (view full) --- 1339 1340 case Branch: 1341 return branchCount(); 1342 1343 default: 1344 return -1; 1345 } 1346 } else { |
1347 int tid = *((*activeThreads).begin()); |
1348 1349 if (fetchStatus[tid] == Running || 1350 fetchStatus[tid] == IcacheAccessComplete || 1351 fetchStatus[tid] == Idle) { 1352 return tid; 1353 } else { 1354 return -1; 1355 } --- 33 unchanged lines hidden (view full) --- 1389} 1390 1391template<class Impl> 1392int 1393DefaultFetch<Impl>::iqCount() 1394{ 1395 std::priority_queue<unsigned> PQ; 1396 |
1397 std::list<unsigned>::iterator threads = (*activeThreads).begin(); |
1398 |
1399 while (threads != (*activeThreads).end()) { |
1400 unsigned tid = *threads++; 1401 1402 PQ.push(fromIEW->iewInfo[tid].iqCount); 1403 } 1404 1405 while (!PQ.empty()) { 1406 1407 unsigned high_pri = PQ.top(); --- 11 unchanged lines hidden (view full) --- 1419} 1420 1421template<class Impl> 1422int 1423DefaultFetch<Impl>::lsqCount() 1424{ 1425 std::priority_queue<unsigned> PQ; 1426 |
1427 |
1428 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1429 1430 while (threads != (*activeThreads).end()) { |
1431 unsigned tid = *threads++; 1432 1433 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1434 } 1435 1436 while (!PQ.empty()) { 1437 1438 unsigned high_pri = PQ.top(); --- 9 unchanged lines hidden (view full) --- 1448 1449 return -1; 1450} 1451 1452template<class Impl> 1453int 1454DefaultFetch<Impl>::branchCount() 1455{ |
1456 std::list<unsigned>::iterator threads = (*activeThreads).begin(); |
1457 panic("Branch Count Fetch policy unimplemented\n"); |
1458 return *threads; |
1459} |