1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 305 unchanged lines hidden (view full) --- 314template<class Impl> 315void 316DefaultFetch<Impl>::initStage() 317{ 318 // Setup PC and nextPC with initial state. 319 for (int tid = 0; tid < numThreads; tid++) { 320 PC[tid] = cpu->readPC(tid); 321 nextPC[tid] = cpu->readNextPC(tid); |
322#if ISA_HAS_DELAY_SLOT |
323 nextNPC[tid] = cpu->readNextNPC(tid); |
324#endif |
325 } 326 327 // Size of cache block. 328 cacheBlkSize = icachePort->peerBlockSize(); 329 330 // Create mask to get rid of offset bits. 331 cacheBlkMask = (cacheBlkSize - 1); 332 --- 166 unchanged lines hidden (view full) --- 499{ 500 // Do branch prediction check here. 501 // A bit of a misnomer...next_PC is actually the current PC until 502 // this function updates it. 503 bool predict_taken; 504 505 if (!inst->isControl()) { 506#if ISA_HAS_DELAY_SLOT |
507 Addr cur_PC = next_PC; 508 next_PC = cur_PC + instSize; //next_NPC; 509 next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize; 510 inst->setPredTarg(next_NPC); |
511#else 512 next_PC = next_PC + instSize; |
513 inst->setPredTarg(next_PC); |
514#endif |
515 return false; 516 } 517 518 int tid = inst->threadNumber; 519#if ISA_HAS_DELAY_SLOT 520 Addr pred_PC = next_PC; 521 predict_taken = branchPred.predict(inst, pred_PC, tid); 522 523 if (predict_taken) { |
524 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid); |
525 } else { |
526 DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid); |
527 } 528 |
529 if (predict_taken) { |
530 next_PC = next_NPC; |
531 next_NPC = pred_PC; |
532 |
533 // Update delay slot info 534 ++delaySlotInfo[tid].numInsts; 535 delaySlotInfo[tid].targetAddr = pred_PC; 536 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid, 537 delaySlotInfo[tid].numInsts); |
538 } else { // !predict_taken 539 if (inst->isCondDelaySlot()) { 540 next_PC = pred_PC; 541 // The delay slot is skipped here if there is on 542 // prediction 543 } else { 544 next_PC = next_NPC; 545 // No need to declare a delay slot here since 546 // there is no for the pred. target to jump 547 } 548 |
549 next_NPC = next_NPC + instSize; 550 } 551#else 552 predict_taken = branchPred.predict(inst, next_PC, tid); 553#endif |
554 555 ++fetchedBranches; 556 557 if (predict_taken) { 558 ++predictedBranches; 559 } 560 561 return predict_taken; --- 104 unchanged lines hidden (view full) --- 666 } 667 668 ret_fault = fault; 669 return true; 670} 671 672template <class Impl> 673inline void |
674DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid) |
675{ |
676 DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n", 677 tid, new_PC); |
678 679 PC[tid] = new_PC; |
680 nextPC[tid] = new_PC + instSize; 681 nextNPC[tid] = new_PC + (2 * instSize); |
682 683 // Clear the icache miss if it's outstanding. 684 if (fetchStatus[tid] == IcacheWaitResponse) { 685 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 686 tid); 687 memReq[tid] = NULL; 688 } 689 --- 9 unchanged lines hidden (view full) --- 699 700 fetchStatus[tid] = Squashing; 701 702 ++fetchSquashCycles; 703} 704 705template<class Impl> 706void |
707DefaultFetch |
708 const InstSeqNum &seq_num, 709 unsigned tid) 710{ 711 DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 712 |
713 doSquash(new_PC, tid); |
714 715#if ISA_HAS_DELAY_SLOT 716 if (seq_num <= delaySlotInfo[tid].branchSeqNum) { 717 delaySlotInfo[tid].numInsts = 0; 718 delaySlotInfo[tid].targetAddr = 0; 719 delaySlotInfo[tid].targetReady = false; 720 } 721#endif --- 29 unchanged lines hidden (view full) --- 751 return ret_val; 752} 753 754template<class Impl> 755typename DefaultFetch<Impl>::FetchStatus 756DefaultFetch<Impl>::updateFetchStatus() 757{ 758 //Check Running |
759 std::list<unsigned>::iterator threads = activeThreads->begin(); 760 std::list<unsigned>::iterator end = activeThreads->end(); |
761 |
762 while (threads != end) { |
763 unsigned tid = *threads++; 764 765 if (fetchStatus[tid] == Running || 766 fetchStatus[tid] == Squashing || 767 fetchStatus[tid] == IcacheAccessComplete) { 768 769 if (_status == Inactive) { 770 DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); --- 17 unchanged lines hidden (view full) --- 788 cpu->deactivateStage(O3CPU::FetchIdx); 789 } 790 791 return Inactive; 792} 793 794template <class Impl> 795void |
796DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num, |
797 bool squash_delay_slot, unsigned tid) 798{ 799 DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 800 |
801 doSquash(new_PC, tid); |
802 803#if ISA_HAS_DELAY_SLOT 804 if (seq_num <= delaySlotInfo[tid].branchSeqNum) { 805 delaySlotInfo[tid].numInsts = 0; 806 delaySlotInfo[tid].targetAddr = 0; 807 delaySlotInfo[tid].targetReady = false; 808 } 809 --- 4 unchanged lines hidden (view full) --- 814 cpu->removeInstsNotInROB(tid, true, 0); 815#endif 816} 817 818template <class Impl> 819void 820DefaultFetch<Impl>::tick() 821{ |
822 std::list<unsigned>::iterator threads = activeThreads->begin(); 823 std::list<unsigned>::iterator end = activeThreads->end(); |
824 bool status_change = false; 825 826 wroteToTimeBuffer = false; 827 |
828 while (threads != end) { |
829 unsigned tid = *threads++; 830 831 // Check the signals for each thread to determine the proper status 832 // for each thread. 833 bool updated_status = checkSignalsAndUpdate(tid); 834 status_change = status_change || updated_status; 835 } 836 --- 87 unchanged lines hidden (view full) --- 924 925#if ISA_HAS_DELAY_SLOT 926 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 927#else 928 InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum; 929#endif 930 // In any case, squash. 931 squash(fromCommit->commitInfo[tid].nextPC, |
932 doneSeqNum, 933 fromCommit->commitInfo[tid].squashDelaySlot, 934 tid); 935 936 // Also check if there's a mispredict that happened. 937 if (fromCommit->commitInfo[tid].branchMispredict) { 938 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 939 fromCommit->commitInfo[tid].nextPC, --- 41 unchanged lines hidden (view full) --- 981 982#if ISA_HAS_DELAY_SLOT 983 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum; 984#else 985 InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum; 986#endif 987 // Squash unless we're already squashing 988 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, |
989 doneSeqNum, 990 tid); 991 992 return true; 993 } 994 } 995 996 if (checkStall(tid) && --- 40 unchanged lines hidden (view full) --- 1037 return; 1038 } 1039 1040 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1041 1042 // The current PC. 1043 Addr &fetch_PC = PC[tid]; 1044 |
1045 // Fault code for memory access. 1046 Fault fault = NoFault; 1047 1048 // If returning from the delay of a cache miss, then update the status 1049 // to running, otherwise do the cache access. Possibly move this up 1050 // to tick() function. 1051 if (fetchStatus[tid] == IcacheAccessComplete) { 1052 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", --- 40 unchanged lines hidden (view full) --- 1093 // If we had a stall due to an icache miss, then return. 1094 if (fetchStatus[tid] == IcacheWaitResponse) { 1095 ++icacheStallCycles; 1096 status_change = true; 1097 return; 1098 } 1099 1100 Addr next_PC = fetch_PC; |
1101 Addr next_NPC = next_PC + instSize; |
1102 InstSeqNum inst_seq; 1103 MachInst inst; 1104 ExtMachInst ext_inst; 1105 // @todo: Fix this hack. 1106 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; 1107 1108 if (fault == NoFault) { 1109 // If the read of the first instruction was successful, then grab the 1110 // instructions from the rest of the cache line and put them into the 1111 // queue heading to decode. 1112 1113 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1114 "decode.\n",tid); 1115 1116 // Need to keep track of whether or not a predicted branch 1117 // ended this fetch block. 1118 bool predicted_branch = false; 1119 |
1120 // Need to keep track of whether or not a delay slot 1121 // instruction has been fetched 1122 |
1123 for (; 1124 offset < cacheBlkSize && 1125 numInst < fetchWidth && |
1126 (!predicted_branch || delaySlotInfo[tid].numInsts > 0); |
1127 ++numInst) { 1128 |
1129 // Get a sequence number. 1130 inst_seq = cpu->getAndIncrementInstSeq(); 1131 1132 // Make sure this is a valid index. 1133 assert(offset <= cacheBlkSize - instSize); 1134 1135 // Get the instruction from the array of the cache line. 1136 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1137 (&cacheData[tid][offset])); 1138 1139#if THE_ISA == ALPHA_ISA 1140 ext_inst = TheISA::makeExtMI(inst, fetch_PC); 1141#elif THE_ISA == SPARC_ISA 1142 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); 1143#elif THE_ISA == MIPS_ISA 1144 ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); 1145#endif 1146 1147 // Create a new DynInst from the instruction fetched. |
1148 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, 1149 next_PC, |
1150 inst_seq, cpu); 1151 instruction->setTid(tid); 1152 1153 instruction->setASID(tid); 1154 1155 instruction->setThreadState(cpu->thread[tid]); 1156 1157 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1158 "[sn:%lli]\n", 1159 tid, instruction->readPC(), inst_seq); 1160 |
1161 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1162 tid, instruction->staticInst->disassemble(fetch_PC)); 1163 1164 instruction->traceData = 1165 Trace::getInstRecord(curTick, cpu->tcBase(tid), 1166 instruction->staticInst, 1167 instruction->readPC()); 1168 |
1169 predicted_branch = lookupAndUpdateNextPC(instruction, next_PC, 1170 next_NPC); |
1171 1172 // Add instruction to the CPU's list of instructions. 1173 instruction->setInstListIt(cpu->addInst(instruction)); 1174 1175 // Write the instruction to the first slot in the queue 1176 // that heads to decode. 1177 toDecode->insts[numInst] = instruction; 1178 1179 toDecode->size++; 1180 1181 // Increment stat of fetched instructions. 1182 ++fetchedInsts; 1183 1184 // Move to the next instruction, unless we have a branch. 1185 fetch_PC = next_PC; |
1186 1187 if (instruction->isQuiesce()) { 1188 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1189 curTick); 1190 fetchStatus[tid] = QuiescePending; 1191 ++numInst; 1192 status_change = true; 1193 break; 1194 } 1195 1196 offset += instSize; |
1197 1198#if ISA_HAS_DELAY_SLOT 1199 if (predicted_branch) { 1200 delaySlotInfo[tid].branchSeqNum = inst_seq; 1201 1202 DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n", 1203 tid, inst_seq); 1204 continue; 1205 } else if (delaySlotInfo[tid].numInsts > 0) { 1206 --delaySlotInfo[tid].numInsts; 1207 1208 // It's OK to set PC to target of branch 1209 if (delaySlotInfo[tid].numInsts == 0) { 1210 delaySlotInfo[tid].targetReady = true; 1211 1212 // Break the looping condition 1213 predicted_branch = true; 1214 } 1215 1216 DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to" 1217 " process.\n", tid, delaySlotInfo[tid].numInsts); 1218 } 1219#endif |
1220 } 1221 1222 if (offset >= cacheBlkSize) { 1223 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1224 "block.\n", tid); 1225 } else if (numInst >= fetchWidth) { 1226 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1227 "for this cycle.\n", tid); |
1228 } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) { |
1229 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1230 "instruction encountered.\n", tid); 1231 } 1232 } 1233 1234 if (numInst > 0) { 1235 wroteToTimeBuffer = true; 1236 } 1237 1238 // Now that fetching is completed, update the PC to signify what the next 1239 // cycle will be. 1240 if (fault == NoFault) { 1241#if ISA_HAS_DELAY_SLOT 1242 if (delaySlotInfo[tid].targetReady && 1243 delaySlotInfo[tid].numInsts == 0) { 1244 // Set PC to target |
1245 PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC 1246 nextPC[tid] = next_PC + instSize; //next_NPC 1247 nextNPC[tid] = next_PC + (2 * instSize); |
1248 1249 delaySlotInfo[tid].targetReady = false; 1250 } else { 1251 PC[tid] = next_PC; 1252 nextPC[tid] = next_NPC; 1253 nextNPC[tid] = next_NPC + instSize; 1254 } 1255 --- 103 unchanged lines hidden (view full) --- 1359 1360 case Branch: 1361 return branchCount(); 1362 1363 default: 1364 return -1; 1365 } 1366 } else { |
1367 std::list<unsigned>::iterator thread = activeThreads->begin(); 1368 assert(thread != activeThreads->end()); 1369 int tid = *thread; |
1370 1371 if (fetchStatus[tid] == Running || 1372 fetchStatus[tid] == IcacheAccessComplete || 1373 fetchStatus[tid] == Idle) { 1374 return tid; 1375 } else { 1376 return -1; 1377 } --- 33 unchanged lines hidden (view full) --- 1411} 1412 1413template<class Impl> 1414int 1415DefaultFetch<Impl>::iqCount() 1416{ 1417 std::priority_queue<unsigned> PQ; 1418 |
1419 std::list<unsigned>::iterator threads = activeThreads->begin(); 1420 std::list<unsigned>::iterator end = activeThreads->end(); |
1421 |
1422 while (threads != end) { |
1423 unsigned tid = *threads++; 1424 1425 PQ.push(fromIEW->iewInfo[tid].iqCount); 1426 } 1427 1428 while (!PQ.empty()) { 1429 1430 unsigned high_pri = PQ.top(); --- 11 unchanged lines hidden (view full) --- 1442} 1443 1444template<class Impl> 1445int 1446DefaultFetch<Impl>::lsqCount() 1447{ 1448 std::priority_queue<unsigned> PQ; 1449 |
1450 std::list<unsigned>::iterator threads = activeThreads->begin(); 1451 std::list<unsigned>::iterator end = activeThreads->end(); |
1452 |
1453 while (threads != end) { |
1454 unsigned tid = *threads++; 1455 1456 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1457 } 1458 1459 while (!PQ.empty()) { 1460 1461 unsigned high_pri = PQ.top(); --- 9 unchanged lines hidden (view full) --- 1471 1472 return -1; 1473} 1474 1475template<class Impl> 1476int 1477DefaultFetch<Impl>::branchCount() 1478{ |
1479 std::list<unsigned>::iterator thread = activeThreads->begin(); 1480 assert(thread != activeThreads->end()); 1481 unsigned tid = *thread; 1482 |
1483 panic("Branch Count Fetch policy unimplemented\n"); |
1484 return 0 * tid; |
1485} |