1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 1100 unchanged lines hidden (view full) --- 1109 1110 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1111 "decode.\n",tid); 1112 1113 // Need to keep track of whether or not a predicted branch 1114 // ended this fetch block. 1115 bool predicted_branch = false; 1116 |
1117 for (; 1118 offset < cacheBlkSize && 1119 numInst < fetchWidth && |
1120 !predicted_branch; |
1121 ++numInst) { 1122 |
1123 // If we're branching after this instruction, quite fetching 1124 // from the same block then. 1125 predicted_branch = 1126 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC); 1127 |
1128 // Get a sequence number. 1129 inst_seq = cpu->getAndIncrementInstSeq(); 1130 1131 // Make sure this is a valid index. 1132 assert(offset <= cacheBlkSize - instSize); 1133 1134 // Get the instruction from the array of the cache line. 1135 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> --- 27 unchanged lines hidden (view full) --- 1163 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1164 tid, instruction->staticInst->disassemble(fetch_PC)); 1165 1166 instruction->traceData = 1167 Trace::getInstRecord(curTick, cpu->tcBase(tid), 1168 instruction->staticInst, 1169 instruction->readPC()); 1170 |
1171 lookupAndUpdateNextPC(instruction, next_PC, next_NPC); |
1172 1173 // Add instruction to the CPU's list of instructions. 1174 instruction->setInstListIt(cpu->addInst(instruction)); 1175 1176 // Write the instruction to the first slot in the queue 1177 // that heads to decode. 1178 toDecode->insts[numInst] = instruction; 1179 1180 toDecode->size++; 1181 1182 // Increment stat of fetched instructions. 1183 ++fetchedInsts; 1184 1185 // Move to the next instruction, unless we have a branch. 1186 fetch_PC = next_PC; |
1187 fetch_NPC = next_NPC; |
1188 1189 if (instruction->isQuiesce()) { 1190 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1191 curTick); 1192 fetchStatus[tid] = QuiescePending; 1193 ++numInst; 1194 status_change = true; 1195 break; 1196 } 1197 1198 offset += instSize; |
1199 } 1200 1201 if (offset >= cacheBlkSize) { 1202 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1203 "block.\n", tid); 1204 } else if (numInst >= fetchWidth) { 1205 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1206 "for this cycle.\n", tid); |
1207 } else if (predicted_branch) { |
1208 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1209 "instruction encountered.\n", tid); 1210 } 1211 } 1212 1213 if (numInst > 0) { 1214 wroteToTimeBuffer = true; 1215 } --- 243 unchanged lines hidden --- |