1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 64 unchanged lines hidden (view full) --- 73 if (status == RangeChange) 74 return; 75 76 panic("DefaultFetch doesn't expect recvStatusChange callback!"); 77} 78 79template<class Impl> 80bool |
81DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt) |
82{ |
83 fetch->processCacheCompletion(pkt); |
84 return true; 85} 86 87template<class Impl> 88void 89DefaultFetch<Impl>::IcachePort::recvRetry() 90{ 91 fetch->recvRetry(); --- 1018 unchanged lines hidden (view full) --- 1110 1111 // Make sure this is a valid index. 1112 assert(offset <= cacheBlkSize - instSize); 1113 1114 // Get the instruction from the array of the cache line. 1115 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1116 (&cacheData[tid][offset])); 1117 |
1118 ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid)); |
1119 1120 // Create a new DynInst from the instruction fetched. 1121 DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, 1122 next_PC, 1123 inst_seq, cpu); 1124 instruction->setTid(tid); 1125 1126 instruction->setASID(tid); --- 324 unchanged lines hidden --- |