1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 95 unchanged lines hidden (view full) --- 104 commitToFetchDelay(params->commitToFetchDelay), 105 fetchWidth(params->fetchWidth), 106 cacheBlocked(false), 107 retryPkt(NULL), 108 retryTid(-1), 109 numThreads(params->numberOfThreads), 110 numFetchingThreads(params->smtNumFetchingThreads), 111 interruptPending(false), |
112 drainPending(false), |
113 switchedOut(false) 114{ 115 if (numThreads > Impl::MaxThreads) 116 fatal("numThreads is not a valid value\n"); 117 118 // Set fetch stage's status to inactive. 119 _status = Inactive; 120 --- 228 unchanged lines hidden (view full) --- 349 unsigned tid = pkt->req->getThreadNum(); 350 351 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 352 353 // Only change the status if it's still waiting on the icache access 354 // to return. 355 if (fetchStatus[tid] != IcacheWaitResponse || 356 pkt->req != memReq[tid] || |
357 isSwitchedOut() || 358 drainPending) { |
359 ++fetchIcacheSquashes; 360 delete pkt->req; 361 delete pkt; 362 return; 363 } 364 365 // Wake up the CPU (if it went to sleep and was waiting on this completion 366 // event). --- 14 unchanged lines hidden (view full) --- 381 // Reset the mem req to NULL. 382 delete pkt->req; 383 delete pkt; 384 memReq[tid] = NULL; 385} 386 387template <class Impl> 388void |
389DefaultFetch<Impl>::drain() |
390{ |
391 // Fetch is ready to drain at any time. 392 cpu->signalDrained(); 393 drainPending = true; |
394} 395 396template <class Impl> 397void |
398DefaultFetch<Impl>::resume() |
399{ |
400 drainPending = false; 401} 402 403template <class Impl> 404void 405DefaultFetch<Impl>::switchOut() 406{ 407 switchedOut = true; |
408 // Branch predictor needs to have its state cleared. 409 branchPred.switchOut(); 410} 411 412template <class Impl> 413void 414DefaultFetch<Impl>::takeOverFrom() 415{ --- 87 unchanged lines hidden (view full) --- 503 504#if FULL_SYSTEM 505 // Flag to say whether or not address is physical addr. 506 unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0; 507#else 508 unsigned flags = 0; 509#endif // FULL_SYSTEM 510 |
511 if (cacheBlocked || (interruptPending && flags == 0) || drainPending) { |
512 // Hold off fetch from getting new instructions when: 513 // Cache is blocked, or 514 // while an interrupt is pending and we're not in PAL mode, or 515 // fetch is switched out. 516 return false; 517 } 518 519 // Align the fetch PC so it's at the start of a cache block. --- 780 unchanged lines hidden --- |