1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 308 unchanged lines hidden (view full) --- 317{ 318 DPRINTF(Fetch, "Setting the fetch queue pointer.\n"); 319 fetchQueue = fq_ptr; 320 321 // Create wire to write information to proper place in fetch queue. 322 toDecode = fetchQueue->getWire(0); 323} 324 |
325template<class Impl> 326void |
327DefaultFetch<Impl>::initStage() 328{ 329 // Setup PC and nextPC with initial state. 330 for (int tid = 0; tid < numThreads; tid++) { 331 PC[tid] = cpu->readPC(tid); 332 nextPC[tid] = cpu->readNextPC(tid); 333 } 334} --- 29 unchanged lines hidden (view full) --- 364 365 // Only switch to IcacheAccessComplete if we're not stalled as well. 366 if (checkStall(tid)) { 367 fetchStatus[tid] = Blocked; 368 } else { 369 fetchStatus[tid] = IcacheAccessComplete; 370 } 371 |
372 // Reset the mem req to NULL. 373 delete pkt->req; 374 delete pkt; 375 memReq[tid] = NULL; 376} 377 378template <class Impl> 379void --- 195 unchanged lines hidden (view full) --- 575 576 PC[tid] = new_PC; 577 nextPC[tid] = new_PC + instSize; 578 579 // Clear the icache miss if it's outstanding. 580 if (fetchStatus[tid] == IcacheWaitResponse) { 581 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 582 tid); |
583 memReq[tid] = NULL; 584 } 585 586 // Get rid of the retrying packet if it was from this thread. 587 if (retryTid == tid) { 588 assert(cacheBlocked); 589 cacheBlocked = false; 590 retryTid = -1; --- 671 unchanged lines hidden --- |