1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 91 unchanged lines hidden (view full) --- 100 cpu->_status = DcacheWaitResponse; 101 cpu->dcache_pkt = NULL; 102 } 103*/ 104} 105 106template<class Impl> 107DefaultFetch<Impl>::DefaultFetch(Params *params) |
108 : mem(params->mem), 109 branchPred(params), |
110 decodeToFetchDelay(params->decodeToFetchDelay), 111 renameToFetchDelay(params->renameToFetchDelay), 112 iewToFetchDelay(params->iewToFetchDelay), 113 commitToFetchDelay(params->commitToFetchDelay), 114 fetchWidth(params->fetchWidth), 115 numThreads(params->numberOfThreads), 116 numFetchingThreads(params->smtNumFetchingThreads), |
117 interruptPending(false), 118 switchedOut(false) |
119{ 120 if (numThreads > Impl::MaxThreads) 121 fatal("numThreads is not a valid value\n"); 122 123 DPRINTF(Fetch, "Fetch constructor called\n"); 124 125 // Set fetch stage's status to inactive. 126 _status = Inactive; --- 31 unchanged lines hidden (view full) --- 158 cacheBlkMask = (cacheBlkSize - 1); 159 160 for (int tid=0; tid < numThreads; tid++) { 161 162 fetchStatus[tid] = Running; 163 164 priorityList.push_back(tid); 165 |
166 memReq[tid] = NULL; |
167 168 // Create space to store a cache line. 169 cacheData[tid] = new uint8_t[cacheBlkSize]; 170 171 stalls[tid].decode = 0; 172 stalls[tid].rename = 0; 173 stalls[tid].iew = 0; 174 stalls[tid].commit = 0; --- 105 unchanged lines hidden (view full) --- 280DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr) 281{ 282 DPRINTF(Fetch, "Setting the CPU pointer.\n"); 283 cpu = cpu_ptr; 284 285 // Name is finally available, so create the port. 286 icachePort = new IcachePort(this); 287 |
288 Port *mem_dport = mem->getPort(""); 289 icachePort->setPeer(mem_dport); 290 mem_dport->setPeer(icachePort); 291 |
292 // Fetch needs to start fetching instructions at the very beginning, 293 // so it must start up in active state. 294 switchToActive(); 295} 296 297template<class Impl> 298void 299DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) --- 56 unchanged lines hidden (view full) --- 356{ 357 unsigned tid = pkt->req->getThreadNum(); 358 359 DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 360 361 // Only change the status if it's still waiting on the icache access 362 // to return. 363 if (fetchStatus[tid] != IcacheWaitResponse || |
364 pkt->req != memReq[tid] || |
365 isSwitchedOut()) { 366 ++fetchIcacheSquashes; |
367 delete pkt->req; |
368 delete pkt; |
369 memReq[tid] = NULL; |
370 return; 371 } 372 373 // Wake up the CPU (if it went to sleep and was waiting on this completion 374 // event). 375 cpu->wakeCPU(); 376 377 DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", --- 8 unchanged lines hidden (view full) --- 386 fetchStatus[tid] = IcacheAccessComplete; 387 } 388 389// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size); 390 391 // Reset the mem req to NULL. 392 delete pkt->req; 393 delete pkt; |
394 memReq[tid] = NULL; |
395} 396 397template <class Impl> 398void 399DefaultFetch<Impl>::switchOut() 400{ 401 // Fetch is ready to switch out at any time. 402 switchedOut = true; --- 114 unchanged lines hidden (view full) --- 517 fetch_PC = icacheBlockAlignPC(fetch_PC); 518 519 // Setup the memReq to do a read of the first instruction's address. 520 // Set the appropriate read size and flags as well. 521 // Build request here. 522 RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags, 523 fetch_PC, cpu->readCpuId(), tid); 524 |
525 memReq[tid] = mem_req; |
526 527 // Translate the instruction request. 528//#if FULL_SYSTEM 529 fault = cpu->translateInstReq(mem_req); 530//#else 531// fault = pTable->translate(memReq[tid]); 532//#endif 533 --- 34 unchanged lines hidden (view full) --- 568 DPRINTF(Fetch, "Doing cache access.\n"); 569 570 lastIcacheStall[tid] = curTick; 571 572 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 573 "response.\n", tid); 574 575 fetchStatus[tid] = IcacheWaitResponse; |
576 } else { 577 delete mem_req; 578 memReq[tid] = NULL; |
579 } 580 581 ret_fault = fault; 582 return true; 583} 584 585template <class Impl> 586inline void --- 4 unchanged lines hidden (view full) --- 591 592 PC[tid] = new_PC; 593 nextPC[tid] = new_PC + instSize; 594 595 // Clear the icache miss if it's outstanding. 596 if (fetchStatus[tid] == IcacheWaitResponse) { 597 DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 598 tid); |
599 // Should I delete this here or when it comes back from the cache? 600// delete memReq[tid]; 601 memReq[tid] = NULL; |
602 } 603 604 fetchStatus[tid] = Squashing; 605 606 ++fetchSquashCycles; 607} 608 609template<class Impl> --- 480 unchanged lines hidden (view full) --- 1090 1091 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1092 1093 fetchStatus[tid] = TrapPending; 1094 status_change = true; 1095 1096 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); 1097#else // !FULL_SYSTEM |
1098 warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); |
1099#endif // FULL_SYSTEM 1100 } 1101} 1102 1103 1104/////////////////////////////////////// 1105// // 1106// SMT FETCH POLICY MAINTAINED HERE // --- 141 unchanged lines hidden --- |