1/* |
2 * Copyright (c) 2010-2014 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 338 unchanged lines hidden (view full) --- 349 pc[tid] = cpu->pcState(tid); 350 fetchOffset[tid] = 0; 351 macroop[tid] = NULL; 352 353 delayedCommit[tid] = false; 354 memReq[tid] = NULL; 355 356 stalls[tid].decode = false; |
357 stalls[tid].drain = false; 358 359 fetchBufferPC[tid] = 0; 360 fetchBufferValid[tid] = false; 361 362 priorityList.push_back(tid); 363 } 364 --- 62 unchanged lines hidden (view full) --- 427 assert(isDrained()); 428 assert(retryPkt == NULL); 429 assert(retryTid == InvalidThreadID); 430 assert(!cacheBlocked); 431 assert(!interruptPending); 432 433 for (ThreadID i = 0; i < numThreads; ++i) { 434 assert(!memReq[i]); |
435 assert(fetchStatus[i] == Idle || stalls[i].drain); 436 } 437 438 branchPred->drainSanityCheck(); 439} 440 441template <class Impl> 442bool --- 225 unchanged lines hidden (view full) --- 668 } else { 669 DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid); 670 DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 671 "response.\n", tid); 672 lastIcacheStall[tid] = curTick(); 673 fetchStatus[tid] = IcacheWaitResponse; 674 } 675 } else { |
676 // Don't send an instruction to decode if it can't handle it. 677 // Asynchronous nature of this function's calling means we have to 678 // check 2 signals to see if decode is stalled. 679 if (!(numInst < fetchWidth) || stalls[tid].decode || 680 fromDecode->decodeBlock[tid]) { |
681 assert(!finishTranslationEvent.scheduled()); 682 finishTranslationEvent.setFault(fault); 683 finishTranslationEvent.setReq(mem_req); 684 cpu->schedule(finishTranslationEvent, 685 cpu->clockEdge(Cycles(1))); 686 return; 687 } 688 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n", --- 105 unchanged lines hidden (view full) --- 794 ret_val = true; 795 } else if (stalls[tid].drain) { 796 assert(cpu->isDraining()); 797 DPRINTF(Fetch,"[tid:%i]: Drain stall detected.\n",tid); 798 ret_val = true; 799 } else if (stalls[tid].decode) { 800 DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 801 ret_val = true; |
802 } 803 804 return ret_val; 805} 806 807template<class Impl> 808typename DefaultFetch<Impl>::FetchStatus 809DefaultFetch<Impl>::updateFetchStatus() --- 125 unchanged lines hidden (view full) --- 935 } 936 937 if (fromDecode->decodeUnblock[tid]) { 938 assert(stalls[tid].decode); 939 assert(!fromDecode->decodeBlock[tid]); 940 stalls[tid].decode = false; 941 } 942 |
943 // Check squash signals from commit. 944 if (fromCommit->commitInfo[tid].squash) { 945 946 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 947 "from commit.\n",tid); 948 // In any case, squash. 949 squash(fromCommit->commitInfo[tid].pc, 950 fromCommit->commitInfo[tid].doneSeqNum, --- 15 unchanged lines hidden (view full) --- 966 967 return true; 968 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 969 // Update the branch predictor if it wasn't a squashed instruction 970 // that was broadcasted. 971 branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid); 972 } 973 |
974 // Check squash signals from decode. 975 if (fromDecode->decodeInfo[tid].squash) { 976 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 977 "from decode.\n",tid); 978 979 // Update the branch predictor. 980 if (fromDecode->decodeInfo[tid].branchMispredict) { 981 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum, --- 626 unchanged lines hidden --- |