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< * Copyright (c) 2010-2012 ARM Limited
---
> * Copyright (c) 2010-2013 ARM Limited
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> cacheBlkSize(cpu->cacheLineSize()),
> cacheBlkMask(cacheBlkSize - 1),
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< cacheData[i] = NULL;
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>
> for (ThreadID tid = 0; tid < numThreads; tid++) {
> // Create space to store a cache line.
> cacheData[tid] = new uint8_t[cacheBlkSize];
> cacheDataPC[tid] = 0;
> cacheDataValid[tid] = false;
> }
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<
< // this CPU could still be unconnected if we are restoring from a
< // checkpoint and this CPU is to be switched in, thus we can only
< // do this here if the instruction port is actually connected, if
< // not we have to do it as part of takeOverFrom.
< if (cpu->getInstPort().isConnected())
< setIcache();
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< DefaultFetch<Impl>::setIcache()
< {
< assert(cpu->getInstPort().isConnected());
<
< // Size of cache block.
< cacheBlkSize = cpu->getInstPort().peerBlockSize();
<
< // Create mask to get rid of offset bits.
< cacheBlkMask = (cacheBlkSize - 1);
<
< for (ThreadID tid = 0; tid < numThreads; tid++) {
< // Create space to store a cache line.
< if (!cacheData[tid])
< cacheData[tid] = new uint8_t[cacheBlkSize];
< cacheDataPC[tid] = 0;
< cacheDataValid[tid] = false;
< }
< }
<
< template<class Impl>
< void