319,321c319
< PC[tid] = cpu->readPC(tid);
< nextPC[tid] = cpu->readNextPC(tid);
< microPC[tid] = cpu->readMicroPC(tid);
---
> pc[tid] = cpu->pcState(tid);
448,450c446
< PC[i] = cpu->readPC(i);
< nextPC[i] = cpu->readNextPC(i);
< microPC[i] = cpu->readMicroPC(i);
---
> pc[i] = cpu->pcState(i);
499,500c495,496
< DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
< Addr &next_NPC, Addr &next_MicroPC)
---
> DefaultFetch<Impl>::lookupAndUpdateNextPC(
> DynInstPtr &inst, TheISA::PCState &nextPC)
508,515c504,505
< if (inst->isMicroop() && !inst->isLastMicroop()) {
< next_MicroPC++;
< } else {
< next_PC = next_NPC;
< next_NPC = next_NPC + instSize;
< next_MicroPC = 0;
< }
< inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
---
> TheISA::advancePC(nextPC, inst->staticInst);
> inst->setPredTarg(nextPC);
520,523d509
< //Assume for now that all control flow is to a different macroop which
< //would reset the micro pc to 0.
< next_MicroPC = 0;
<
525,526c511
< Addr pred_PC = next_PC;
< predict_taken = branchPred.predict(inst, pred_PC, tid);
---
> predict_taken = branchPred.predict(inst, nextPC, tid);
529,530c514,515
< DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %#x.\n",
< tid, inst->seqNum, pred_PC);
---
> DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n",
> tid, inst->seqNum, nextPC);
536,552c521,523
< #if ISA_HAS_DELAY_SLOT
< next_PC = next_NPC;
< if (predict_taken)
< next_NPC = pred_PC;
< else
< next_NPC += instSize;
< #else
< if (predict_taken)
< next_PC = pred_PC;
< else
< next_PC += instSize;
< next_NPC = next_PC + instSize;
< #endif
<
< DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %#x and then %#x.\n",
< tid, inst->seqNum, next_PC, next_NPC);
< inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
---
> DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
> tid, inst->seqNum, nextPC);
> inst->setPredTarg(nextPC);
671,672c642
< DefaultFetch<Impl>::doSquash(const Addr &new_PC,
< const Addr &new_NPC, const Addr &new_microPC, ThreadID tid)
---
> DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
674,675c644,645
< DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
< tid, new_PC, new_NPC);
---
> DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
> tid, newPC);
677,679c647
< PC[tid] = new_PC;
< nextPC[tid] = new_NPC;
< microPC[tid] = new_microPC;
---
> pc[tid] = newPC;
706,707c674
< DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
< const Addr &new_MicroPC,
---
> DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
710c677
< DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
---
> DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
712c679
< doSquash(new_PC, new_NPC, new_MicroPC, tid);
---
> doSquash(newPC, tid);
787,788c754
< DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
< const Addr &new_MicroPC,
---
> DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
791c757
< DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
---
> DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
793c759
< doSquash(new_PC, new_NPC, new_MicroPC, tid);
---
> doSquash(newPC, tid);
906,908c872
< squash(fromCommit->commitInfo[tid].nextPC,
< fromCommit->commitInfo[tid].nextNPC,
< fromCommit->commitInfo[tid].nextMicroPC,
---
> squash(fromCommit->commitInfo[tid].pc,
915c879
< fromCommit->commitInfo[tid].nextPC,
---
> fromCommit->commitInfo[tid].pc,
958,960c922,923
< DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
< fromDecode->decodeInfo[tid].nextPC,
< fromDecode->decodeInfo[tid].nextNPC);
---
> TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
> DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
963,964d925
< fromDecode->decodeInfo[tid].nextNPC,
< fromDecode->decodeInfo[tid].nextMicroPC,
1019,1021c980
< Addr fetch_PC = PC[tid];
< Addr fetch_NPC = nextPC[tid];
< Addr fetch_MicroPC = microPC[tid];
---
> TheISA::PCState fetchPC = pc[tid];
1037,1038c996
< "instruction, starting at PC %08p.\n",
< tid, fetch_PC);
---
> "instruction, starting at PC %s.\n", tid, fetchPC);
1040c998
< bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
---
> bool fetch_success = fetchCacheLine(fetchPC.instAddr(), fault, tid);
1078,1080c1036
< Addr next_PC = fetch_PC;
< Addr next_NPC = fetch_NPC;
< Addr next_MicroPC = fetch_MicroPC;
---
> TheISA::PCState nextPC = fetchPC;
1085,1086d1040
< // @todo: Fix this hack.
< unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1091a1046,1050
> //XXX Masking out pal mode bit. This will break x86. Alpha needs
> //to pull the pal mode bit ouf ot the instruction address.
> unsigned offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid];
> assert(offset < cacheBlkSize);
>
1107,1115d1065
< // If we're branching after this instruction, quite fetching
< // from the same block then.
< predicted_branch =
< (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
< if (predicted_branch) {
< DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
< fetch_PC, fetch_NPC);
< }
<
1125c1075
< predecoder.moreBytes(fetch_PC, fetch_PC, inst);
---
> predecoder.moreBytes(fetchPC, fetchPC.instAddr(), inst);
1127,1128c1077,1078
< ext_inst = predecoder.getExtMachInst();
< staticInst = StaticInstPtr(ext_inst, fetch_PC);
---
> ext_inst = predecoder.getExtMachInst(fetchPC);
> staticInst = StaticInstPtr(ext_inst, fetchPC.instAddr());
1134c1084
< staticInst = macroop->fetchMicroop(fetch_MicroPC);
---
> staticInst = macroop->fetchMicroop(fetchPC.microPC());
1144,1145c1094
< fetch_PC, fetch_NPC, fetch_MicroPC,
< next_PC, next_NPC, next_MicroPC,
---
> fetchPC, nextPC,
1153,1155c1102,1104
< DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
< "[sn:%lli]\n", tid, instruction->readPC(),
< instruction->readMicroPC(), inst_seq);
---
> DPRINTF(Fetch, "[tid:%i]: Instruction PC %s (%d) created "
> "[sn:%lli]\n", tid, instruction->pcState(),
> instruction->microPC(), inst_seq);
1159,1160c1108,1110
< DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
< tid, instruction->staticInst->disassemble(fetch_PC));
---
> DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
> instruction->staticInst->
> disassemble(fetchPC.instAddr()));
1165,1166c1115
< instruction->staticInst, instruction->readPC(),
< macroop, instruction->readMicroPC());
---
> instruction->staticInst, fetchPC, macroop);
1171c1120,1122
< ///FIXME This needs to be more robust in dealing with delay slots
---
> // If we're branching after this instruction, quite fetching
> // from the same block then.
> predicted_branch = fetchPC.branching();
1173c1124,1127
< lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
---
> lookupAndUpdateNextPC(instruction, nextPC);
> if (predicted_branch) {
> DPRINTF(Fetch, "Branch detected with PC = %s\n", fetchPC);
> }
1188,1190c1142
< fetch_PC = next_PC;
< fetch_NPC = next_NPC;
< fetch_MicroPC = next_MicroPC;
---
> fetchPC = nextPC;
1205c1157,1158
< offset += instSize;
---
> //XXX Masking out pal mode bit.
> offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid];
1227,1230c1180,1181
< PC[tid] = next_PC;
< nextPC[tid] = next_NPC;
< microPC[tid] = next_MicroPC;
< DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
---
> pc[tid] = nextPC;
> DPRINTF(Fetch, "[tid:%i]: Setting PC to %s.\n", tid, nextPC);
1248,1250c1199
< DynInstPtr instruction = new DynInst(ext_inst,
< fetch_PC, fetch_NPC, fetch_MicroPC,
< next_PC, next_NPC, next_MicroPC,
---
> DynInstPtr instruction = new DynInst(ext_inst, fetchPC, nextPC,
1252c1201,1202
< instruction->setPredTarg(next_NPC, next_NPC + instSize, 0);
---
> TheISA::advancePC(nextPC, instruction->staticInst);
> instruction->setPredTarg(nextPC);
1275,1276c1225,1226
< DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
< tid, fault->name(), PC[tid]);
---
> DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s",
> tid, fault->name(), pc[tid]);