32,34d31
< #include <algorithm>
< #include <cstring>
<
53a51,52
> #include <algorithm>
>
378c377
< memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
---
> memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
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< const InstSeqNum &seq_num,
< bool squash_delay_slot, unsigned tid)
---
> const InstSeqNum &seq_num, unsigned tid)
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< #if ISA_HAS_DELAY_SLOT
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< cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
< #else
< // Tell the CPU to remove any instructions that are not in the ROB.
< cpu->removeInstsNotInROB(tid, true, 0);
< #endif
---
> cpu->removeInstsNotInROB(tid);
900,905d892
<
< #if ISA_HAS_DELAY_SLOT
< InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
< #else
< InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
< #endif
909,910c896
< doneSeqNum,
< fromCommit->commitInfo[tid].squashDelaySlot,
---
> fromCommit->commitInfo[tid].doneSeqNum,
959,963d944
< #if ISA_HAS_DELAY_SLOT
< InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
< #else
< InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
< #endif
970c951
< doneSeqNum,
---
> fromDecode->decodeInfo[tid].doneSeqNum,
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< predecoder.moreBytes(fetch_PC, fetch_PC, inst);
---
> predecoder.moreBytes(fetch_PC, 0, inst);
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< #if TRACING_ON
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< #else
< instruction->traceData = NULL;
< #endif
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< #if !ISA_HAS_DELAY_SLOT
< // predicted_branch |=
< #endif
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< #if ISA_HAS_DELAY_SLOT
< DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
< #else
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< #endif