322d321
< #if ISA_HAS_DELAY_SLOT
324d322
< #endif
507,510c505,507
< Addr cur_PC = next_PC;
< next_PC = cur_PC + instSize; //next_NPC;
< next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
< inst->setPredTarg(next_NPC);
---
> next_PC = next_NPC;
> next_NPC = next_NPC + instSize;
> inst->setPredTarg(next_PC, next_NPC);
513c510
< inst->setPredTarg(next_PC);
---
> inst->setPredTarg(next_PC, next_PC + sizeof(TheISA::MachInst));
514a512
> inst->setPredTaken(false);
524c522
< DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
---
> DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken.\n", tid);
526c524
< DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
---
> DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid);
528a527
> next_PC = next_NPC;
530d528
< next_PC = next_NPC;
532d529
<
538,548c535
< } else { // !predict_taken
< if (inst->isCondDelaySlot()) {
< next_PC = pred_PC;
< // The delay slot is skipped here if there is on
< // prediction
< } else {
< next_PC = next_NPC;
< // No need to declare a delay slot here since
< // there is no for the pred. target to jump
< }
<
---
> } else {
553a541,544
> DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n",
> tid, next_PC, next_NPC);
> inst->setPredTarg(next_PC, next_NPC);
> inst->setPredTaken(predict_taken);
674c665,666
< DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
---
> DefaultFetch<Impl>::doSquash(const Addr &new_PC,
> const Addr &new_NPC, unsigned tid)
676,677c668,669
< DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
< tid, new_PC);
---
> DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
> tid, new_PC, new_NPC);
680,681c672,673
< nextPC[tid] = new_PC + instSize;
< nextNPC[tid] = new_PC + (2 * instSize);
---
> nextPC[tid] = new_NPC;
> nextNPC[tid] = new_NPC + instSize;
707c699
< DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
---
> DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
713c705
< doSquash(new_PC, tid);
---
> doSquash(new_PC, new_NPC, tid);
759,760c751
< std::list<unsigned>::iterator threads = activeThreads->begin();
< std::list<unsigned>::iterator end = activeThreads->end();
---
> std::list<unsigned>::iterator threads = (*activeThreads).begin();
762c753,754
< while (threads != end) {
---
> while (threads != (*activeThreads).end()) {
>
796c788,789
< DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
---
> DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
> const InstSeqNum &seq_num,
801c794
< doSquash(new_PC, tid);
---
> doSquash(new_PC, new_NPC, tid);
822,823c815
< std::list<unsigned>::iterator threads = activeThreads->begin();
< std::list<unsigned>::iterator end = activeThreads->end();
---
> std::list<unsigned>::iterator threads = (*activeThreads).begin();
828c820
< while (threads != end) {
---
> while (threads != (*activeThreads).end()) {
931a924
> fromCommit->commitInfo[tid].nextNPC,
988a982
> fromDecode->decodeInfo[tid].nextNPC,
1044a1039,1040
> Addr &fetch_NPC = nextPC[tid];
>
1101c1097,1098
< Addr next_NPC = next_PC + instSize;
---
> Addr next_NPC = fetch_NPC;
>
1120,1122d1116
< // Need to keep track of whether or not a delay slot
< // instruction has been fetched
<
1126c1120
< (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
---
> !predicted_branch;
1128a1123,1127
> // If we're branching after this instruction, quite fetching
> // from the same block then.
> predicted_branch =
> (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
>
1148,1149c1147,1149
< DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
< next_PC,
---
> DynInstPtr instruction = new DynInst(ext_inst,
> fetch_PC, fetch_NPC,
> next_PC, next_NPC,
1160a1161,1162
> DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
>
1169,1170c1171
< predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
< next_NPC);
---
> lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
1185a1187
> fetch_NPC = next_NPC;
1197,1219d1198
<
< #if ISA_HAS_DELAY_SLOT
< if (predicted_branch) {
< delaySlotInfo[tid].branchSeqNum = inst_seq;
<
< DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
< tid, inst_seq);
< continue;
< } else if (delaySlotInfo[tid].numInsts > 0) {
< --delaySlotInfo[tid].numInsts;
<
< // It's OK to set PC to target of branch
< if (delaySlotInfo[tid].numInsts == 0) {
< delaySlotInfo[tid].targetReady = true;
<
< // Break the looping condition
< predicted_branch = true;
< }
<
< DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
< " process.\n", tid, delaySlotInfo[tid].numInsts);
< }
< #endif
1228c1207
< } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
---
> } else if (predicted_branch) {
1245,1247c1224,1226
< PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
< nextPC[tid] = next_PC + instSize; //next_NPC
< nextNPC[tid] = next_PC + (2 * instSize);
---
> PC[tid] = next_PC;
> nextPC[tid] = next_NPC;
> nextNPC[tid] = next_NPC + instSize;
1280,1281c1259,1261
< DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
< next_PC,
---
> DynInstPtr instruction = new DynInst(ext_inst,
> fetch_PC, fetch_NPC,
> next_PC, next_NPC,
1283c1263
< instruction->setPredTarg(next_PC + instSize);
---
> instruction->setPredTarg(next_PC, next_NPC);
1367,1369c1347
< std::list<unsigned>::iterator thread = activeThreads->begin();
< assert(thread != activeThreads->end());
< int tid = *thread;
---
> int tid = *((*activeThreads).begin());
1419,1420c1397
< std::list<unsigned>::iterator threads = activeThreads->begin();
< std::list<unsigned>::iterator end = activeThreads->end();
---
> std::list<unsigned>::iterator threads = (*activeThreads).begin();
1422c1399
< while (threads != end) {
---
> while (threads != (*activeThreads).end()) {
1450,1451d1426
< std::list<unsigned>::iterator threads = activeThreads->begin();
< std::list<unsigned>::iterator end = activeThreads->end();
1453c1428,1430
< while (threads != end) {
---
> std::list<unsigned>::iterator threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
1479,1482c1456
< std::list<unsigned>::iterator thread = activeThreads->begin();
< assert(thread != activeThreads->end());
< unsigned tid = *thread;
<
---
> std::list<unsigned>::iterator threads = (*activeThreads).begin();
1484c1458
< return 0 * tid;
---
> return *threads;